Re: [Qemu-devel] [RFC PATCH] arm: implement cache/shareability attribute bits for PAR registers

[Peter Maydell]

On 19 October 2017 at 18:04, Andrew Baumann
<address@hidden> wrote:
>> From: Peter Maydell [mailto:address@hidden
>> Sent: Thursday, 19 October 2017 09:51
>>
>> On 18 October 2017 at 01:16, Andrew Baumann
>> <address@hidden> wrote:
>> Hi; thanks for this patch. Looks like you forgot to add your
>> signed-off-by line.
>
> Thanks for the review!
>
> I didn’t sign the patch, because it wasn't ready to go in, and my (limited)
> understanding of the protocol is that that's one of the things you're
> certifying in a signature.

Usually the way we do it is that if you have something that isn't
ready to go in, you mark it as [RFC], but you leave your signed-off-by
tag on it. That way if you should (hypothetically) disappear without
having time to update the RFC to a working version, somebody else
can start with the code you posted to the list and work on it.

Signed-off-by is really saying "I did this work and it's ok for this
to be distributed under the project's license", rather than a claim
about the quality of the code.

>> So you want the page table walk functions to directly fill in
>> the information about cacheability and shareability, including
>> doing lookups in MAIR registers (or PRRR/NMRR registers, which
>> QEMU stores in the same CPUState fields, but they have a different
>> format.)
>
> I agree. FWIW, the original reason for doing it here was that I
> didn't want to slow down the normal page-table walk with additional
> logic to compute the attributes, which isn't necessary for a TLB
> fill. If we're adding extra out parameters to the walker, then I
> can make those optional and skip computing them when the parameter
> is NULL.

Sure, though I think that if we've got to the point of having to
do a page table walk then we're already very much in the slow path,
so I don't mind if we just fill out the attributes every time.

thanks
-- PMM