Re: [Qemu-devel] [PATCH] hw/pci-host: Fix x86 Host Bridges 64bit PCI hole

[Laszlo Ersek]

On 10/20/17 08:55, Gerd Hoffmann wrote:
>   Hi,
> 
>>> commit message says:
>>>
>>> <quote>
>>>      It turns out that some 32 bit windows guests crash
>>>      if 64 bit PCI hole size is >2G.
>>> </quote>
>>>
>>> Why this suddenly isn't a problem any more?
>>>
>>
>> I suppose it is, so we need a way to turn it "off".
> 
> Or have machine types behave differently, i.e. give q35 a large 64bit
> hole and leave pc as-is.

*If* we make it dependent on machine types at all, then please also make
it versioned for Q35.

> 
> Devices with that large bars are most likely pci express anyway ...
> 
>> This is how I started, however Eduardo and (and maybe Michael ?)
>> where against letting the upper management software to deal with
>> such a low low level detail. They simply can't take such a decision.
>> This is why the property you mentioned is not ever linked
>> in code anywhere! It is simply not implemented and not used.
> 
> Makes sense.
> 
> BTW:  Is it safe to just assume 40 bits physical is going to work?  My
> workstation:
> 
> model name      : Intel(R) Core(TM) i7-7700K CPU @ 4.20GHz
> address sizes   : 39 bits physical, 48 bits virtual
> 
> Does this imply ept is limited 39 bits physical too?

Very good point to raise; "39 bits physical" on your workstation *does*
imply that EPT is limited exactly the same way. I had run into this very
problem while working on 64GB+ RAM enablement in OVMF. (Back then my
laptop had: "address sizes : 36 bits physical, 48 bits virtual".)

Thanks,
Laszlo