[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 10/43] xilinx_spips: Add support for 4 byte addresses
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 10/43] xilinx_spips: Add support for 4 byte addresses in the LQSPI |
Date: |
Wed, 13 Dec 2017 18:12:08 +0000 |
From: Francisco Iglesias <address@hidden>
Add support for 4 byte addresses in the LQSPI and correct LQSPI_CFG_SEP_BUS.
Signed-off-by: Francisco Iglesias <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Edgar E. Iglesias <address@hidden>
Tested-by: Edgar E. Iglesias <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/ssi/xilinx_spips.c | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index 878b17e..ab54da8 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -92,8 +92,9 @@
#define R_LQSPI_CFG_RESET 0x03A002EB
#define LQSPI_CFG_LQ_MODE (1U << 31)
#define LQSPI_CFG_TWO_MEM (1 << 30)
-#define LQSPI_CFG_SEP_BUS (1 << 30)
+#define LQSPI_CFG_SEP_BUS (1 << 29)
#define LQSPI_CFG_U_PAGE (1 << 28)
+#define LQSPI_CFG_ADDR4 (1 << 27)
#define LQSPI_CFG_MODE_EN (1 << 25)
#define LQSPI_CFG_MODE_WIDTH 8
#define LQSPI_CFG_MODE_SHIFT 16
@@ -702,6 +703,9 @@ static void lqspi_load_cache(void *opaque, hwaddr addr)
fifo8_push(&s->tx_fifo, s->regs[R_LQSPI_CFG] & LQSPI_CFG_INST_CODE);
/* read address */
DB_PRINT_L(0, "pushing read address %06x\n", flash_addr);
+ if (s->regs[R_LQSPI_CFG] & LQSPI_CFG_ADDR4) {
+ fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 24));
+ }
fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 16));
fifo8_push(&s->tx_fifo, (uint8_t)(flash_addr >> 8));
fifo8_push(&s->tx_fifo, (uint8_t)flash_addr);
--
2.7.4
- [Qemu-devel] [PULL 11/43] xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done, (continued)
- [Qemu-devel] [PULL 11/43] xilinx_spips: Don't set TX FIFO UNDERFLOW at cmd done, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 04/43] m25p80: Add support for n25q512a11 and n25q512a13, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 03/43] m25p80: Add support for BRRD/BRWR and BULK_ERASE (0x60), Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 02/43] m25p80: Add support for SST READ ID 0x90/0xAB commands, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 09/43] xilinx_spips: Add support for zero pumping, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 14/43] hw/intc/arm_gicv3_its: Don't call post_load on reset, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 15/43] hw/intc/arm_gicv3_its: Implement a minimalist reset, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 20/43] target/arm: Add missing M profile case to regime_is_user(), Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 08/43] xilinx_spips: Make tx/rx_data_bytes more generic and reusable, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 07/43] xilinx_spips: Add support for RX discard and RX drain, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 10/43] xilinx_spips: Add support for 4 byte addresses in the LQSPI,
Peter Maydell <=
- [Qemu-devel] [PULL 17/43] hw/intc/arm_gicv3_its: Implement full reset, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 18/43] target/arm: Handle SPSEL and current stack being out of sync in MSP/PSP reads, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 12/43] xilinx_spips: Add support for the ZynqMP Generic QSPI, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 13/43] xlnx-zcu102: Add support for the ZynqMP QSPI, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 21/43] target/arm: Split M profile MNegPri mmu index into user and priv, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 22/43] target/arm: Create new arm_v7m_mmu_idx_for_secstate_and_priv(), Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 25/43] target/arm: Provide fault type enum and FSR conversion functions, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 27/43] target/arm: Convert get_phys_addr_v5() to not return FSC values, Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 23/43] target/arm: Factor MPU lookup code out of get_phys_addr_pmsav8(), Peter Maydell, 2017/12/13
- [Qemu-devel] [PULL 30/43] target/arm: Convert get_phys_addr_pmsav5() to not return FSC values, Peter Maydell, 2017/12/13