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[Qemu-devel] [PULL 01/12] target-ppc: optimize cmp translation
From: |
David Gibson |
Subject: |
[Qemu-devel] [PULL 01/12] target-ppc: optimize cmp translation |
Date: |
Mon, 8 Jan 2018 16:53:37 +1100 |
From: "address@hidden" <address@hidden>
We know that only one bit (in addition to SO) is going to be set in
the condition register, so do two movconds instead of three setconds,
three shifts and two ORs.
For ppc64-linux-user, the code size reduction is around 5% and the
performance improvement slightly less than 10%. For softmmu, the
improvement is around 5%.
Signed-off-by: Paolo Bonzini <address@hidden>
Signed-off-by: David Gibson <address@hidden>
---
target/ppc/translate.c | 29 ++++++++++++-----------------
1 file changed, 12 insertions(+), 17 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index 4075fc8589..8a6bd329d0 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -605,27 +605,22 @@ static opc_handler_t invalid_handler = {
static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
{
TCGv t0 = tcg_temp_new();
- TCGv_i32 t1 = tcg_temp_new_i32();
-
- tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
-
- tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
- tcg_gen_trunc_tl_i32(t1, t0);
- tcg_gen_shli_i32(t1, t1, CRF_LT_BIT);
- tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
+ TCGv t1 = tcg_temp_new();
+ TCGv_i32 t = tcg_temp_new_i32();
- tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
- tcg_gen_trunc_tl_i32(t1, t0);
- tcg_gen_shli_i32(t1, t1, CRF_GT_BIT);
- tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
+ tcg_gen_movi_tl(t0, CRF_EQ);
+ tcg_gen_movi_tl(t1, CRF_LT);
+ tcg_gen_movcond_tl((s ? TCG_COND_LT : TCG_COND_LTU), t0, arg0, arg1, t1,
t0);
+ tcg_gen_movi_tl(t1, CRF_GT);
+ tcg_gen_movcond_tl((s ? TCG_COND_GT : TCG_COND_GTU), t0, arg0, arg1, t1,
t0);
- tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
- tcg_gen_trunc_tl_i32(t1, t0);
- tcg_gen_shli_i32(t1, t1, CRF_EQ_BIT);
- tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
+ tcg_gen_trunc_tl_i32(t, t0);
+ tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
+ tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t);
tcg_temp_free(t0);
- tcg_temp_free_i32(t1);
+ tcg_temp_free(t1);
+ tcg_temp_free_i32(t);
}
static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
--
2.14.3
- [Qemu-devel] [PULL 00/12] ppc-for-2.12 queue 20180108, David Gibson, 2018/01/08
- [Qemu-devel] [PULL 01/12] target-ppc: optimize cmp translation,
David Gibson <=
- [Qemu-devel] [PULL 04/12] sm501: Add some more unimplemented registers, David Gibson, 2018/01/08
- [Qemu-devel] [PULL 03/12] sm501: Add panel hardware cursor registers also to read function, David Gibson, 2018/01/08
- [Qemu-devel] [PULL 06/12] spapr_pci: use warn_report(), David Gibson, 2018/01/08
- [Qemu-devel] [PULL 09/12] target/ppc: more use of the PPC_*() macros, David Gibson, 2018/01/08
- [Qemu-devel] [PULL 05/12] ppc4xx_i2c: Implement basic I2C functions, David Gibson, 2018/01/08
- [Qemu-devel] [PULL 10/12] Update dtc to fix compilation problem on Mac OS 10.6, David Gibson, 2018/01/08
- [Qemu-devel] [PULL 11/12] hw/ppc: Remove the deprecated spapr-pci-vfio-host-bridge device, David Gibson, 2018/01/08
- [Qemu-devel] [PULL 12/12] spapr: Correct compatibility mode setting for hotplugged CPUs, David Gibson, 2018/01/08