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Re: [Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation |
Date: |
Thu, 11 Jan 2018 07:47:50 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.5.2 |
On 01/10/2018 06:21 PM, Michael Clark wrote:
> TCG code generation for the RV32IMAFDC and RV64IMAFDC. The QEMU
> RISC-V code generator has complete coverage for the Base ISA v2.2,
> Privileged ISA v1.9.1 and Privileged ISA v1.10:
>
> - RISC-V Instruction Set Manual Volume I: User-Level ISA Version 2.2
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.9.1
> - RISC-V Instruction Set Manual Volume II: Privileged ISA Version 1.10
>
> Signed-off-by: Michael Clark <address@hidden>
> ---
> target/riscv/instmap.h | 377 +++++++++
> target/riscv/translate.c | 1982
> ++++++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 2359 insertions(+)
> create mode 100644 target/riscv/instmap.h
> create mode 100644 target/riscv/translate.c
While there is forward progress within translate.c, it would seem that quite a
lot of my v1 comments are not yet addressed.
Also,
> + if (!riscv_has_ext(env, RVC)) {
You may not access env in this way. Any code generation differences must be
computable from either unchanging values on the cpu or tb->flags. MISA is not
unchanging -- you allow runtime modification.
Again, the partial patch I saw from Stefan would fix this.
r~
- Re: [Qemu-devel] [PATCH v3 21/21] RISC-V Build Infrastructure, (continued)
- [Qemu-devel] [PATCH v3 14/21] SiFive RISC-V PLIC Block, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 04/21] RISC-V Disassembler, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 19/21] SiFive Freedom E300 RISC-V Machine, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 15/21] RISC-V Spike Machines, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 20/21] SiFive Freedom U500 RISC-V Machine, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation, Michael Clark, 2018/01/10
- Re: [Qemu-devel] [PATCH v3 08/21] RISC-V TCG Code Generation,
Richard Henderson <=
- Re: [Qemu-devel] [PATCH v3 00/21] RISC-V QEMU Port Submission v3, no-reply, 2018/01/10