[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH 3/7] i386: Add spec-ctrl CPUID bit
From: |
Gonglei (Arei) |
Subject: |
Re: [Qemu-devel] [PATCH 3/7] i386: Add spec-ctrl CPUID bit |
Date: |
Sat, 13 Jan 2018 03:04:44 +0000 |
> -----Original Message-----
> From: Qemu-devel
> [mailto:address@hidden On
> Behalf Of Eduardo Habkost
> Sent: Tuesday, January 09, 2018 11:45 PM
> To: address@hidden
> Cc: Paolo Bonzini
> Subject: [Qemu-devel] [PATCH 3/7] i386: Add spec-ctrl CPUID bit
>
> Add the feature name and a CPUID_7_0_EDX_SPEC_CTRL macro.
>
> Signed-off-by: Eduardo Habkost <address@hidden>
> ---
> target/i386/cpu.h | 1 +
> target/i386/cpu.c | 2 +-
> 2 files changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 07f47997d6..de387c1311 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -667,6 +667,7 @@ typedef uint32_t
> FeatureWordArray[FEATURE_WORDS];
>
> #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural
> Network Instructions */
> #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply
> Accumulation Single Precision */
> +#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Speculation Control
> */
>
> #define CPUID_XSAVE_XSAVEOPT (1U << 0)
> #define CPUID_XSAVE_XSAVEC (1U << 1)
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
> index 9f4f949899..1be1642eb2 100644
> --- a/target/i386/cpu.c
> +++ b/target/i386/cpu.c
> @@ -459,7 +459,7 @@ static FeatureWordInfo
> feature_word_info[FEATURE_WORDS] = {
> NULL, NULL, NULL, NULL,
> NULL, NULL, NULL, NULL,
> NULL, NULL, NULL, NULL,
> - NULL, NULL, NULL, NULL,
> + NULL, NULL, "spec-ctrl", NULL,
> NULL, NULL, NULL, NULL,
> },
> .cpuid_eax = 7,
> --
> 2.14.3
>
Don't we need to pass-through cupid_7_edx to guest when configuring '-cpu host'?
Otherwise how guests use IBPB/IBRS/STIPB capabilities?
Thanks,
-Gonglei
- [Qemu-devel] [PATCH 0/7] CPU model updates for CVE-2017-5715 (Spectre variant #2), Eduardo Habkost, 2018/01/09
- [Qemu-devel] [PATCH 4/7] i386: Add FEAT_8000_0008_EBX CPUID feature word, Eduardo Habkost, 2018/01/09
- [Qemu-devel] [PATCH 6/7] [RFC] i386: Add EPYC-IBPB CPU model, Eduardo Habkost, 2018/01/09
- [Qemu-devel] [PATCH 5/7] i386: Add new -IBRS versions of Intel CPU models, Eduardo Habkost, 2018/01/09
- [Qemu-devel] [PATCH 7/7] [RFC] i386: Add PCID to {Westmere, SandyBridge, IvyBridge}-IBRS, Eduardo Habkost, 2018/01/09
- Re: [Qemu-devel] [PATCH 0/7] CPU model updates for CVE-2017-5715 (Spectre variant #2), no-reply, 2018/01/10
- Re: [Qemu-devel] [PATCH 0/7] CPU model updates for CVE-2017-5715 (Spectre variant #2), Eduardo Habkost, 2018/01/12
- Re: [Qemu-devel] [PATCH 0/7] CPU model updates for CVE-2017-5715 (Spectre variant #2), Eduardo Habkost, 2018/01/15