[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
Re: [Qemu-devel] [PATCH v2 12/21] RISC-V HART Array
From: |
Igor Mammedov |
Subject: |
Re: [Qemu-devel] [PATCH v2 12/21] RISC-V HART Array |
Date: |
Mon, 15 Jan 2018 14:19:26 +0100 |
On Wed, 10 Jan 2018 15:46:31 -0800
Michael Clark <address@hidden> wrote:
> Holds the state of a heterogenous array of RISC-V hardware threads.
>
> Signed-off-by: Michael Clark <address@hidden>
> ---
> hw/riscv/riscv_hart.c | 95
> +++++++++++++++++++++++++++++++++++++++++++
> include/hw/riscv/riscv_hart.h | 45 ++++++++++++++++++++
> 2 files changed, 140 insertions(+)
> create mode 100644 hw/riscv/riscv_hart.c
> create mode 100644 include/hw/riscv/riscv_hart.h
>
> diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
> new file mode 100644
> index 0000000..a7e079e
> --- /dev/null
> +++ b/hw/riscv/riscv_hart.c
> @@ -0,0 +1,95 @@
> +/*
> + * QEMU RISCV Hart Array
> + *
> + * Copyright (c) 2017 SiFive, Inc.
> + *
> + * Holds the state of a heterogenous array of RISC-V harts
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> copy
> + * of this software and associated documentation files (the "Software"), to
> deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "qemu/osdep.h"
> +#include "qapi/error.h"
> +#include "hw/sysbus.h"
> +#include "target/riscv/cpu.h"
> +#include "hw/riscv/riscv_hart.h"
> +
> +static Property riscv_harts_props[] = {
> + DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1),
> + DEFINE_PROP_STRING("cpu-model", RISCVHartArrayState, cpu_model),
suggest to rename it to cpu-type/cpu_type since it's used as such,
new code shouldn't use cpu_model anywhere except of foo_cpu_class_by_name()
callback.
> + DEFINE_PROP_END_OF_LIST(),
> +};
> +
> +static void riscv_harts_cpu_reset(void *opaque)
> +{
> + RISCVCPU *cpu = opaque;
> + cpu_reset(CPU(cpu));
> +}
> +
> +static void riscv_harts_realize(DeviceState *dev, Error **errp)
> +{
> + RISCVHartArrayState *s = RISCV_HART_ARRAY(dev);
> + Error *err = NULL;
> + int n;
> +
> + s->harts = g_new0(RISCVCPU, s->num_harts);
> +
> + for (n = 0; n < s->num_harts; n++) {
> +
> + object_initialize(&s->harts[n], sizeof(RISCVCPU), s->cpu_model);
> + s->harts[n].env.mhartid = n;
> + object_property_add_child(OBJECT(s), "harts[*]",
> OBJECT(&s->harts[n]),
> + &error_abort);
> + qemu_register_reset(riscv_harts_cpu_reset, &s->harts[n]);
> + object_property_set_bool(OBJECT(&s->harts[n]), true,
> + "realized", &err);
> + if (err) {
> + error_propagate(errp, err);
> + return;
> + }
> + }
> +}
> +
> +static void riscv_harts_class_init(ObjectClass *klass, void *data)
> +{
> + DeviceClass *dc = DEVICE_CLASS(klass);
> +
> + dc->props = riscv_harts_props;
> + dc->realize = riscv_harts_realize;
> +}
> +
> +static void riscv_harts_init(Object *obj)
> +{
> + /* RISCVHartArrayState *s = SIFIVE_COREPLEX(obj); */
> +}
> +
> +static const TypeInfo riscv_harts_info = {
> + .name = TYPE_RISCV_HART_ARRAY,
> + .parent = TYPE_SYS_BUS_DEVICE,
> + .instance_size = sizeof(RISCVHartArrayState),
> + .instance_init = riscv_harts_init,
> + .class_init = riscv_harts_class_init,
> +};
> +
> +static void riscv_harts_register_types(void)
> +{
> + type_register_static(&riscv_harts_info);
> +}
> +
> +type_init(riscv_harts_register_types)
> diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
> new file mode 100644
> index 0000000..c45e987
> --- /dev/null
> +++ b/include/hw/riscv/riscv_hart.h
> @@ -0,0 +1,45 @@
> +/*
> + * QEMU RISC-V Hart Array interface
> + *
> + * Copyright (c) 2017 SiFive, Inc.
> + *
> + * Holds the state of a heterogenous array of RISC-V harts
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a
> copy
> + * of this software and associated documentation files (the "Software"), to
> deal
> + * in the Software without restriction, including without limitation the
> rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
> FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#ifndef HW_RISCV_HART_H
> +#define HW_RISCV_HART_H
> +
> +#define TYPE_RISCV_HART_ARRAY "riscv.hart_array"
> +
> +#define RISCV_HART_ARRAY(obj) \
> + OBJECT_CHECK(RISCVHartArrayState, (obj), TYPE_RISCV_HART_ARRAY)
> +
> +typedef struct RISCVHartArrayState {
> + /*< private >*/
> + SysBusDevice parent_obj;
> +
> + /*< public >*/
> + uint32_t num_harts;
> + char *cpu_model;
> + RISCVCPU *harts;
> +} RISCVHartArrayState;
> +
> +#endif
- [Qemu-devel] [PATCH v2 00/21] RISC-V QEMU Port Submission v2, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v2 01/21] RISC-V Maintainers, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v2 02/21] RISC-V ELF Machine Definition, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v2 07/21] RISC-V GDB Stub, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v2 06/21] RISC-V FPU Support, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v2 03/21] RISC-V CPU Core Definition, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v2 12/21] RISC-V HART Array, Michael Clark, 2018/01/10
- Re: [Qemu-devel] [PATCH v2 12/21] RISC-V HART Array,
Igor Mammedov <=
- [Qemu-devel] [PATCH v2 05/21] RISC-V CPU Helpers, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v2 09/21] RISC-V Physical Memory Protection, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v2 13/21] SiFive RISC-V CLINT Block, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v2 11/21] RISC-V HTIF Console, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v2 18/21] SiFive RISC-V PRCI Block, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v2 17/21] SiFive RISC-V UART Device, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v2 14/21] SiFive RISC-V PLIC Block, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v2 21/21] RISC-V Build Infrastructure, Michael Clark, 2018/01/10
- [Qemu-devel] [PATCH v2 19/21] SiFive Freedom E300 RISC-V Machine, Michael Clark, 2018/01/10