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[Qemu-devel] [PATCH v9 17/26] target/arm: Use vector infrastructure for
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v9 17/26] target/arm: Use vector infrastructure for aa64 mov/not/neg |
Date: |
Mon, 15 Jan 2018 19:33:55 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.c | 43 ++++++++++++++++++++++++++++++++++++++-----
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 572af456d1..bc14c28e71 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -85,6 +85,7 @@ typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32);
typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32);
/* Note that the gvec expanders operate on offsets + sizes. */
+typedef void GVecGen2Fn(unsigned, uint32_t, uint32_t, uint32_t, uint32_t);
typedef void GVecGen3Fn(unsigned, uint32_t, uint32_t,
uint32_t, uint32_t, uint32_t);
@@ -4579,14 +4580,19 @@ static void handle_fp_1src_double(DisasContext *s, int
opcode, int rd, int rn)
TCGv_i64 tcg_op;
TCGv_i64 tcg_res;
+ switch (opcode) {
+ case 0x0: /* FMOV */
+ tcg_gen_gvec_mov(0, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ 8, vec_full_reg_size(s));
+ return;
+ }
+
fpst = get_fpstatus_ptr();
tcg_op = read_fp_dreg(s, rn);
tcg_res = tcg_temp_new_i64();
switch (opcode) {
- case 0x0: /* FMOV */
- tcg_gen_mov_i64(tcg_res, tcg_op);
- break;
case 0x1: /* FABS */
gen_helper_vfp_absd(tcg_res, tcg_op);
break;
@@ -9153,6 +9159,12 @@ static void disas_simd_3same_logic(DisasContext *s,
uint32_t insn)
gvec_fn = tcg_gen_gvec_andc;
goto do_fn;
case 2: /* ORR */
+ if (rn == rm) { /* MOV */
+ tcg_gen_gvec_mov(0, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ is_q ? 16 : 8, vec_full_reg_size(s));
+ return;
+ }
gvec_fn = tcg_gen_gvec_or;
goto do_fn;
case 3: /* ORN */
@@ -10032,6 +10044,7 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
int rmode = -1;
TCGv_i32 tcg_rmode;
TCGv_ptr tcg_fpstatus;
+ GVecGen2Fn *gvec_fn;
switch (opcode) {
case 0x0: /* REV64, REV32 */
@@ -10040,8 +10053,7 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
return;
case 0x5: /* CNT, NOT, RBIT */
if (u && size == 0) {
- /* NOT: adjust size so we can use the 64-bits-at-a-time loop. */
- size = 3;
+ /* NOT */
break;
} else if (u && size == 1) {
/* RBIT */
@@ -10293,6 +10305,27 @@ static void disas_simd_two_reg_misc(DisasContext *s,
uint32_t insn)
tcg_rmode = NULL;
}
+ switch (opcode) {
+ case 0x5:
+ if (u && size == 0) { /* NOT */
+ gvec_fn = tcg_gen_gvec_not;
+ goto do_fn;
+ }
+ break;
+ case 0xb:
+ if (u) { /* NEG */
+ gvec_fn = tcg_gen_gvec_neg;
+ goto do_fn;
+ }
+ break;
+
+ do_fn:
+ gvec_fn(size, vec_full_reg_offset(s, rd),
+ vec_full_reg_offset(s, rn),
+ is_q ? 16 : 8, vec_full_reg_size(s));
+ return;
+ }
+
if (size == 3) {
/* All 64-bit element operations can be shared with scalar 2misc */
int pass;
--
2.14.3
- [Qemu-devel] [PATCH v9 08/26] tcg: Add generic vector ops for multiplication, (continued)
- [Qemu-devel] [PATCH v9 08/26] tcg: Add generic vector ops for multiplication, Richard Henderson, 2018/01/15
- [Qemu-devel] [PATCH v9 09/26] tcg: Add generic vector ops for extension, Richard Henderson, 2018/01/15
- [Qemu-devel] [PATCH v9 07/26] tcg: Add generic vector ops for comparisons, Richard Henderson, 2018/01/15
- [Qemu-devel] [PATCH v9 10/26] tcg: Add generic helpers for saturating arithmetic, Richard Henderson, 2018/01/15
- [Qemu-devel] [PATCH v9 11/26] tcg: Loosen vec_gen_op* typecheck rules, Richard Henderson, 2018/01/15
- [Qemu-devel] [PATCH v9 13/26] tcg: Add generic vector helpers with a scalar variable operand, Richard Henderson, 2018/01/15
- [Qemu-devel] [PATCH v9 12/26] tcg: Add generic vector helpers with a scalar immediate operand, Richard Henderson, 2018/01/15
- [Qemu-devel] [PATCH v9 14/26] tcg/optimize: Handle vector opcodes during optimize, Richard Henderson, 2018/01/15
- [Qemu-devel] [PATCH v9 15/26] target/arm: Align vector registers, Richard Henderson, 2018/01/15
- [Qemu-devel] [PATCH v9 16/26] target/arm: Use vector infrastructure for aa64 add/sub/logic, Richard Henderson, 2018/01/15
- [Qemu-devel] [PATCH v9 17/26] target/arm: Use vector infrastructure for aa64 mov/not/neg,
Richard Henderson <=
- [Qemu-devel] [PATCH v9 18/26] target/arm: Use vector infrastructure for aa64 dup/movi, Richard Henderson, 2018/01/15
- [Qemu-devel] [PATCH v9 19/26] target/arm: Use vector infrastructure for aa64 zip/uzp/trn/xtn, Richard Henderson, 2018/01/15
- [Qemu-devel] [PATCH v9 21/26] target/arm: Use vector infrastructure for aa64 compares, Richard Henderson, 2018/01/15
- [Qemu-devel] [PATCH v9 20/26] target/arm: Use vector infrastructure for aa64 constant shifts, Richard Henderson, 2018/01/15
- [Qemu-devel] [PATCH v9 23/26] target/arm: Use vector infrastructure for aa64 widening shifts, Richard Henderson, 2018/01/15
- [Qemu-devel] [PATCH v9 22/26] target/arm: Use vector infrastructure for aa64 multiplies, Richard Henderson, 2018/01/15
- [Qemu-devel] [PATCH v9 24/26] target/arm: Use vector infrastructure for aa64 orr/bic immediate, Richard Henderson, 2018/01/15
- [Qemu-devel] [PATCH v9 26/26] tcg/aarch64: Add vector operations, Richard Henderson, 2018/01/15
- [Qemu-devel] [PATCH v9 25/26] tcg/i386: Add vector operations, Richard Henderson, 2018/01/15
- Re: [Qemu-devel] [PATCH v9 00/26] tcg: generic vector operations, no-reply, 2018/01/15