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[Qemu-devel] [PATCH v3 10/22] fpu/softfloat: move the extract functions
From: |
Alex Bennée |
Subject: |
[Qemu-devel] [PATCH v3 10/22] fpu/softfloat: move the extract functions to the top of the file |
Date: |
Wed, 24 Jan 2018 13:13:03 +0000 |
This is pure code-motion during re-factoring as the helpers will be
needed earlier.
Signed-off-by: Alex Bennée <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
---
v2
- fix minor white space nit
---
fpu/softfloat.c | 120 +++++++++++++++++++++++++-------------------------------
1 file changed, 54 insertions(+), 66 deletions(-)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 3a4ab1355f..297e48f5c9 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -132,6 +132,60 @@ static inline flag extractFloat16Sign(float16 a)
return float16_val(a)>>15;
}
+/*----------------------------------------------------------------------------
+| Returns the fraction bits of the single-precision floating-point value `a'.
+*----------------------------------------------------------------------------*/
+
+static inline uint32_t extractFloat32Frac(float32 a)
+{
+ return float32_val(a) & 0x007FFFFF;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the exponent bits of the single-precision floating-point value `a'.
+*----------------------------------------------------------------------------*/
+
+static inline int extractFloat32Exp(float32 a)
+{
+ return (float32_val(a) >> 23) & 0xFF;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the sign bit of the single-precision floating-point value `a'.
+*----------------------------------------------------------------------------*/
+
+static inline flag extractFloat32Sign(float32 a)
+{
+ return float32_val(a) >> 31;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the fraction bits of the double-precision floating-point value `a'.
+*----------------------------------------------------------------------------*/
+
+static inline uint64_t extractFloat64Frac(float64 a)
+{
+ return float64_val(a) & LIT64(0x000FFFFFFFFFFFFF);
+}
+
+/*----------------------------------------------------------------------------
+| Returns the exponent bits of the double-precision floating-point value `a'.
+*----------------------------------------------------------------------------*/
+
+static inline int extractFloat64Exp(float64 a)
+{
+ return (float64_val(a) >> 52) & 0x7FF;
+}
+
+/*----------------------------------------------------------------------------
+| Returns the sign bit of the double-precision floating-point value `a'.
+*----------------------------------------------------------------------------*/
+
+static inline flag extractFloat64Sign(float64 a)
+{
+ return float64_val(a) >> 63;
+}
+
/*----------------------------------------------------------------------------
| Takes a 64-bit fixed-point value `absZ' with binary point between bits 6
| and 7, and returns the properly rounded 32-bit integer corresponding to the
@@ -299,39 +353,6 @@ static int64_t roundAndPackUint64(flag zSign, uint64_t
absZ0,
return absZ0;
}
-/*----------------------------------------------------------------------------
-| Returns the fraction bits of the single-precision floating-point value `a'.
-*----------------------------------------------------------------------------*/
-
-static inline uint32_t extractFloat32Frac( float32 a )
-{
-
- return float32_val(a) & 0x007FFFFF;
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the exponent bits of the single-precision floating-point value `a'.
-*----------------------------------------------------------------------------*/
-
-static inline int extractFloat32Exp(float32 a)
-{
-
- return ( float32_val(a)>>23 ) & 0xFF;
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the sign bit of the single-precision floating-point value `a'.
-*----------------------------------------------------------------------------*/
-
-static inline flag extractFloat32Sign( float32 a )
-{
-
- return float32_val(a)>>31;
-
-}
-
/*----------------------------------------------------------------------------
| If `a' is denormal and we are in flush-to-zero mode then set the
| input-denormal exception and return zero. Otherwise just return the value.
@@ -492,39 +513,6 @@ static float32
}
-/*----------------------------------------------------------------------------
-| Returns the fraction bits of the double-precision floating-point value `a'.
-*----------------------------------------------------------------------------*/
-
-static inline uint64_t extractFloat64Frac( float64 a )
-{
-
- return float64_val(a) & LIT64( 0x000FFFFFFFFFFFFF );
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the exponent bits of the double-precision floating-point value `a'.
-*----------------------------------------------------------------------------*/
-
-static inline int extractFloat64Exp(float64 a)
-{
-
- return ( float64_val(a)>>52 ) & 0x7FF;
-
-}
-
-/*----------------------------------------------------------------------------
-| Returns the sign bit of the double-precision floating-point value `a'.
-*----------------------------------------------------------------------------*/
-
-static inline flag extractFloat64Sign( float64 a )
-{
-
- return float64_val(a)>>63;
-
-}
-
/*----------------------------------------------------------------------------
| If `a' is denormal and we are in flush-to-zero mode then set the
| input-denormal exception and return zero. Otherwise just return the value.
--
2.15.1
- [Qemu-devel] [PATCH v3 05/22] include/fpu/softfloat: implement float16_abs helper, (continued)
- [Qemu-devel] [PATCH v3 05/22] include/fpu/softfloat: implement float16_abs helper, Alex Bennée, 2018/01/24
- [Qemu-devel] [PATCH v3 06/22] include/fpu/softfloat: implement float16_chs helper, Alex Bennée, 2018/01/24
- [Qemu-devel] [PATCH v3 09/22] fpu/softfloat: improve comments on ARM NaN propagation, Alex Bennée, 2018/01/24
- [Qemu-devel] [PATCH v3 07/22] include/fpu/softfloat: implement float16_set_sign helper, Alex Bennée, 2018/01/24
- [Qemu-devel] [PATCH v3 08/22] include/fpu/softfloat: add some float16 constants, Alex Bennée, 2018/01/24
- [Qemu-devel] [PATCH v3 13/22] fpu/softfloat: re-factor mul, Alex Bennée, 2018/01/24
- [Qemu-devel] [PATCH v3 10/22] fpu/softfloat: move the extract functions to the top of the file,
Alex Bennée <=
- [Qemu-devel] [PATCH v3 12/22] fpu/softfloat: re-factor add/sub, Alex Bennée, 2018/01/24
- [Qemu-devel] [PATCH v3 14/22] fpu/softfloat: re-factor div, Alex Bennée, 2018/01/24
- [Qemu-devel] [PATCH v3 11/22] fpu/softfloat: define decompose structures, Alex Bennée, 2018/01/24
- [Qemu-devel] [PATCH v3 18/22] fpu/softfloat: re-factor int/uint to float, Alex Bennée, 2018/01/24
- [Qemu-devel] [PATCH v3 20/22] fpu/softfloat: re-factor minmax, Alex Bennée, 2018/01/24