Re: [Qemu-devel] [PATCH v6 5/5] target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support

[Peter Maydell]

On 7 February 2018 at 14:57, Alex Bennée <address@hidden> wrote:
>
> Ard Biesheuvel <address@hidden> writes:
>
>> Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to
>> AArch64 user mode emulation.
>
> So another problem I've come across is I can't turn this off. I ended up
> doing that in my FP16 series because otherwise existing RISU tests get
> broken. However having an optional flag for each little set of
> instructions seems overkill.

Why do the existing tests break? Are they checking UNDEF
for previously-reserved bits of the encoding space?

> Have you run any RISU tests? If you want you can add this to the
> aarch64.risu to generate some test patterns.

I wrote some risu patterns for testing these. I was going
to send the patch out tomorrow...

(I used the tag A64_C82 rather than A64_V.)

thanks
-- PMM