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From: | Alex Bennée |
Subject: | Re: [Qemu-devel] [PATCH v6 5/5] target/arm: enable user-mode SHA-3, SM3, SM4 and SHA-512 instruction support |
Date: | Wed, 07 Feb 2018 15:17:40 +0000 |
User-agent: | mu4e 1.0-alpha3; emacs 26.0.91 |
Peter Maydell <address@hidden> writes: > On 7 February 2018 at 14:57, Alex Bennée <address@hidden> wrote: >> >> Ard Biesheuvel <address@hidden> writes: >> >>> Add support for the new ARMv8.2 SHA-3, SM3, SM4 and SHA-512 instructions to >>> AArch64 user mode emulation. >> >> So another problem I've come across is I can't turn this off. I ended up >> doing that in my FP16 series because otherwise existing RISU tests get >> broken. However having an optional flag for each little set of >> instructions seems overkill. > > Why do the existing tests break? Are they checking UNDEF > for previously-reserved bits of the encoding space? Yeah. Maybe the easiest solution is to find the undefs and re-generate everything. > >> Have you run any RISU tests? If you want you can add this to the >> aarch64.risu to generate some test patterns. > > I wrote some risu patterns for testing these. I was going > to send the patch out tomorrow... > > (I used the tag A64_C82 rather than A64_V.) Ohh that is a useful use for that tag... > > thanks > -- PMM -- Alex Bennée
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