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Re: [Qemu-devel] [PATCH v2 23/32] arm/helper.c: re-factor recpe and add
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v2 23/32] arm/helper.c: re-factor recpe and add recepe_f16 |
Date: |
Fri, 9 Feb 2018 09:54:58 -0800 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 02/08/2018 09:31 AM, Alex Bennée wrote:
> +float16 HELPER(recpe_f16)(float16 input, void *fpstp)
> +{
> + float_status *fpst = fpstp;
> + float16 f16 = float16_squash_input_denormal(input, fpst);
> + uint32_t f16_val = float16_val(f16);
> + uint32_t f16_sign = float16_is_neg(f16);
> + int f16_exp = extract32(f16_val, 10, 5);
> + uint32_t f16_frac = extract32(f16_val, 0, 10);
> + uint64_t f64_frac;
> +
> + if (float16_is_any_nan(f16)) {
> + float16 nan = f16;
> + if (float16_is_signaling_nan(f16, fpst)) {
> + float_raise(float_flag_invalid, fpst);
> + nan = float16_maybe_silence_nan(f16, fpst);
> + }
> + if (fpst->default_nan_mode) {
> + nan = float16_default_nan(fpst);
> + }
> + return nan;
> + } else if (float16_is_infinity(f16)) {
> + return float16_set_sign(float16_zero, float16_is_neg(f16));
> + } else if (float16_is_zero(f16)) {
> + float_raise(float_flag_divbyzero, fpst);
> + return float16_set_sign(float16_infinity, float16_is_neg(f16));
> + } else if (float16_abs(f16) < (1 << 8)) {
> + /* Abs(value) < 2.0^-14 */
The pseudocode I'm looking at says 2.0^-16. But I think the code is right --
this is checking for two zero bits at the top of a denormal, so that is
2.0^(-14-2).
> + float_raise(float_flag_overflow | float_flag_inexact, fpst);
> + if (round_to_inf(fpst, f16_sign)) {
> + return float16_set_sign(float16_infinity, f16_sign);
> + } else {
> + return float16_set_sign(float16_maxnorm, f16_sign);
> + }
> + /* FP16 has it's own flag FZ16 flag which is in a separate fpst*/
> + } else if (f16_exp >= 14 && fpst->flush_to_zero) {
(1) The comment is confusing.
(a) It's placement within the previous IF is not helpful,
(b) Why mention the separate fpst, begging the question of
where it is? We're using it, of course, so...
(2) The exponent is still biased, so this isn't 2.0^14 you're testing.
> } else if (f32_exp >= 253 && fpst->flush_to_zero) {
E.g. the single-precision version tests (2^)126 + (bias)127.
r~
- Re: [Qemu-devel] [PATCH v2 18/32] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16, (continued)
- [Qemu-devel] [PATCH v2 27/32] arm/helper.c: re-factor rsqrte and add rsqrte_f16, Alex Bennée, 2018/02/08
- [Qemu-devel] [PATCH v2 22/32] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/08
- [Qemu-devel] [PATCH v2 30/32] arm/translate-a64: add all FP16 ops in simd_scalar_pairwise, Alex Bennée, 2018/02/08
- [Qemu-devel] [PATCH v2 29/32] arm/translate-a64: add FP16 FMOV to simd_mod_imm, Alex Bennée, 2018/02/08
- [Qemu-devel] [PATCH v2 23/32] arm/helper.c: re-factor recpe and add recepe_f16, Alex Bennée, 2018/02/08
- Re: [Qemu-devel] [PATCH v2 23/32] arm/helper.c: re-factor recpe and add recepe_f16,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 14/32] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16, Alex Bennée, 2018/02/08
- [Qemu-devel] [PATCH v2 28/32] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/08
- [Qemu-devel] [PATCH v2 16/32] arm/translate-a64: add FP16 x2 ops for simd_indexed, Alex Bennée, 2018/02/08
- [Qemu-devel] [PATCH v2 25/32] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/08
- Re: [Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions, no-reply, 2018/02/08
- Re: [Qemu-devel] [PATCH v2 00/32] Add ARMv8.2 half-precision functions, no-reply, 2018/02/08