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[Qemu-devel] [PULL 19/48] sdhci: add qtest to check the SD Spec version
From: |
Paolo Bonzini |
Subject: |
[Qemu-devel] [PULL 19/48] sdhci: add qtest to check the SD Spec version |
Date: |
Tue, 13 Feb 2018 13:00:23 +0100 |
From: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Stefan Hajnoczi <address@hidden>
Message-Id: <address@hidden>
---
tests/sdhci-test.c | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/tests/sdhci-test.c b/tests/sdhci-test.c
index 6fa3ddb..3e9a5bf 100644
--- a/tests/sdhci-test.c
+++ b/tests/sdhci-test.c
@@ -54,6 +54,19 @@ typedef struct QSDHCI {
};
} QSDHCI;
+static uint32_t sdhci_readl(QSDHCI *s, uint32_t reg)
+{
+ uint32_t val;
+
+ if (s->pci.dev) {
+ qpci_memread(s->pci.dev, s->mem_bar, reg, &val, sizeof(val));
+ } else {
+ val = qtest_readl(global_qtest, s->addr + reg);
+ }
+
+ return val;
+}
+
static uint64_t sdhci_readq(QSDHCI *s, uint32_t reg)
{
uint64_t val;
@@ -76,6 +89,16 @@ static void sdhci_writeq(QSDHCI *s, uint32_t reg, uint64_t
val)
}
}
+static void check_specs_version(QSDHCI *s, uint8_t version)
+{
+ uint32_t v;
+
+ v = sdhci_readl(s, SDHC_HCVER);
+ v &= 0xff;
+ v += 1;
+ g_assert_cmpuint(v, ==, version);
+}
+
static void check_capab_capareg(QSDHCI *s, uint64_t expec_capab)
{
uint64_t capab;
@@ -164,6 +187,7 @@ static void test_machine(const void *data)
s = machine_start(test);
+ check_specs_version(s, test->sdhci.version);
check_capab_capareg(s, test->sdhci.capab.reg);
check_capab_readonly(s);
check_capab_sdma(s, test->sdhci.capab.sdma);
--
1.8.3.1
- [Qemu-devel] [PULL 16/48] sdhci: add check_capab_readonly() qtest, (continued)
- [Qemu-devel] [PULL 16/48] sdhci: add check_capab_readonly() qtest, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 15/48] sdhci: add qtest to check the SD capabilities register, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 23/48] sdhci: check the Spec v1 capabilities correctness, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 27/48] hw/arm/exynos4210: access the 64-bit capareg with qdev_prop_set_uint64(), Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 20/48] sdhci: add a 'spec_version property' (default to v2), Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 21/48] sdhci: use a numeric value for the default CAPAB register, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 22/48] sdhci: simplify sdhci_get_fifolen(), Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 28/48] hw/arm/exynos4210: add a comment about a very similar SDHCI (Spec. v2), Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 36/48] hw/arm/bcm2835_peripherals: implement SDHCI Spec v3, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 12/48] build-sys: remove useless extra*flags variables, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 19/48] sdhci: add qtest to check the SD Spec version,
Paolo Bonzini <=
- [Qemu-devel] [PULL 32/48] sdhci: implement the Host Control 2 register (tuning sequence), Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 25/48] sdhci: Fix 64-bit ADMA2, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 34/48] sdhci: implement UHS-I voltage switch, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 35/48] sdhci: implement CMD/DAT[] fields in the Present State register, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 33/48] sdbus: add trace events, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 29/48] hw/arm/xilinx_zynq: fix the capabilities register to match the datasheet, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 31/48] sdhci: rename the hostctl1 register, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 40/48] hw/arm/xilinx_zynqmp: enable the UHS-I mode, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 37/48] hw/arm/bcm2835_peripherals: change maximum block size to 1kB, Paolo Bonzini, 2018/02/13
- [Qemu-devel] [PULL 38/48] hw/arm/fsl-imx6: implement SDHCI Spec. v3, Paolo Bonzini, 2018/02/13