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[Qemu-devel] [PATCH v2 41/67] target/arm: Implement FDUP/DUP
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 41/67] target/arm: Implement FDUP/DUP |
Date: |
Sat, 17 Feb 2018 10:22:57 -0800 |
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-sve.c | 35 +++++++++++++++++++++++++++++++++++
target/arm/sve.decode | 8 ++++++++
2 files changed, 43 insertions(+)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index 4b92a55c21..7571d02237 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -2939,6 +2939,41 @@ static void trans_WHILE(DisasContext *s, arg_WHILE *a,
uint32_t insn)
tcg_temp_free_i32(t3);
}
+/*
+ *** SVE Integer Wide Immediate - Unpredicated Group
+ */
+
+static void trans_FDUP(DisasContext *s, arg_FDUP *a, uint32_t insn)
+{
+ unsigned vsz = vec_full_reg_size(s);
+ int dofs = vec_full_reg_offset(s, a->rd);
+ uint64_t imm;
+
+ if (a->esz == 0) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ /* Decode the VFP immediate. */
+ imm = vfp_expand_imm(a->esz, a->imm);
+ imm = dup_const(a->esz, imm);
+
+ tcg_gen_gvec_dup64i(dofs, vsz, vsz, imm);
+}
+
+static void trans_DUP_i(DisasContext *s, arg_DUP_i *a, uint32_t insn)
+{
+ unsigned vsz = vec_full_reg_size(s);
+ int dofs = vec_full_reg_offset(s, a->rd);
+
+ if (a->esz == 0 && extract32(insn, 13, 1)) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ tcg_gen_gvec_dup64i(dofs, vsz, vsz, dup_const(a->esz, a->imm));
+}
+
/*
*** SVE Memory - 32-bit Gather and Unsized Contiguous Group
*/
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index b5bc7e9546..ea1bfe7579 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -622,6 +622,14 @@ CTERM 00100101 1 sf:1 1 rm:5 001000 rn:5 ne:1
0000
# SVE integer compare scalar count and limit
WHILE 00100101 esz:2 1 rm:5 000 sf:1 u:1 1 rn:5 eq:1 rd:4
+### SVE Integer Wide Immediate - Unpredicated Group
+
+# SVE broadcast floating-point immediate (unpredicated)
+FDUP 00100101 esz:2 111 00 1110 imm:8 rd:5
+
+# SVE broadcast integer immediate (unpredicated)
+DUP_i 00100101 esz:2 111 00 011 . ........ rd:5 imm=%sh8_i8s
+
### SVE Memory - 32-bit Gather and Unsized Contiguous Group
# SVE load predicate register
--
2.14.3
- [Qemu-devel] [PATCH v2 37/67] target/arm: Implement SVE Integer Compare - Immediate Group, (continued)
- [Qemu-devel] [PATCH v2 37/67] target/arm: Implement SVE Integer Compare - Immediate Group, Richard Henderson, 2018/02/17
- [Qemu-devel] [PATCH v2 39/67] target/arm: Implement SVE Predicate Count Group, Richard Henderson, 2018/02/17
- [Qemu-devel] [PATCH v2 38/67] target/arm: Implement SVE Partition Break Group, Richard Henderson, 2018/02/17
- [Qemu-devel] [PATCH v2 40/67] target/arm: Implement SVE Integer Compare - Scalars Group, Richard Henderson, 2018/02/17
- [Qemu-devel] [PATCH v2 41/67] target/arm: Implement FDUP/DUP,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 42/67] target/arm: Implement SVE Integer Wide Immediate - Unpredicated Group, Richard Henderson, 2018/02/17
- [Qemu-devel] [PATCH v2 43/67] target/arm: Implement SVE Floating Point Arithmetic - Unpredicated Group, Richard Henderson, 2018/02/17
- [Qemu-devel] [PATCH v2 44/67] target/arm: Implement SVE Memory Contiguous Load Group, Richard Henderson, 2018/02/17
- [Qemu-devel] [PATCH v2 45/67] target/arm: Implement SVE Memory Contiguous Store Group, Richard Henderson, 2018/02/17