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[Qemu-devel] [PATCH] tcg/i386: Support INDEX_op_dup2_vec for -m32
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH] tcg/i386: Support INDEX_op_dup2_vec for -m32 |
Date: |
Wed, 21 Feb 2018 13:00:42 -0800 |
Unknown why -m32 was passing with gcc but not clang; it should have
failed for both. This would be used for tcg_gen_dup_i64_vec, and
visible with the right TB and an aarch64 guest.
Reported-by: Max Reitz <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
tcg/i386/tcg-target.inc.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/tcg/i386/tcg-target.inc.c b/tcg/i386/tcg-target.inc.c
index 45943e540c..5e8f59dc47 100644
--- a/tcg/i386/tcg-target.inc.c
+++ b/tcg/i386/tcg-target.inc.c
@@ -2696,6 +2696,12 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_x86_packus_vec:
insn = packus_insn[vece];
goto gen_simd;
+#if TCG_TARGET_REG_BITS == 32
+ case INDEX_op_dup2_vec:
+ /* Constraints have already placed both 32-bit inputs in xmm regs. */
+ insn = OPC_PUNPCKLDQ;
+ goto gen_simd;
+#endif
gen_simd:
tcg_debug_assert(insn != OPC_UD2);
if (type == TCG_TYPE_V256) {
@@ -3045,6 +3051,9 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode
op)
case INDEX_op_x86_vperm2i128_vec:
case INDEX_op_x86_punpckl_vec:
case INDEX_op_x86_punpckh_vec:
+#if TCG_TARGET_REG_BITS == 32
+ case INDEX_op_dup2_vec:
+#endif
return &x_x_x;
case INDEX_op_dup_vec:
case INDEX_op_shli_vec:
--
2.14.3
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