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[Qemu-devel] [PULL 01/32] target/arm: Fix register definitions for VMIDR
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 01/32] target/arm: Fix register definitions for VMIDR and VMPIDR |
Date: |
Thu, 22 Feb 2018 15:22:36 +0000 |
The register definitions for VMIDR and VMPIDR have separate
reginfo structs for the AArch32 and AArch64 registers. However
the 32-bit versions are wrong:
* they use offsetof instead of offsetoflow32 to mark where
the 32-bit value lives in the uint64_t CPU state field
* they don't mark themselves as ARM_CP_ALIAS
In particular this means that if you try to use an Arm guest CPU
which enables EL2 on a big-endian host it will assert at reset:
target/arm/cpu.c:114: cp_reg_check_reset: Assertion `oldvalue == newvalue'
failed.
because the reset of the 32-bit register writes to the top
half of the uint64_t.
Correct the errors in the structures.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
---
This is necessary for 'make check' to pass on big endian
systems with the 'raspi3' board enabled, which is the
first board which has an EL2-enabled-by-default CPU.
---
target/arm/helper.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 32e4fd4732..c5bc69b961 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5069,8 +5069,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
{ .name = "VPIDR", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
.access = PL2_RW, .accessfn = access_el3_aa32ns,
- .resetvalue = cpu->midr,
- .fieldoffset = offsetof(CPUARMState, cp15.vpidr_el2) },
+ .resetvalue = cpu->midr, .type = ARM_CP_ALIAS,
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.vpidr_el2) },
{ .name = "VPIDR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 0,
.access = PL2_RW, .resetvalue = cpu->midr,
@@ -5078,8 +5078,8 @@ void register_cp_regs_for_features(ARMCPU *cpu)
{ .name = "VMPIDR", .state = ARM_CP_STATE_AA32,
.cp = 15, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
.access = PL2_RW, .accessfn = access_el3_aa32ns,
- .resetvalue = vmpidr_def,
- .fieldoffset = offsetof(CPUARMState, cp15.vmpidr_el2) },
+ .resetvalue = vmpidr_def, .type = ARM_CP_ALIAS,
+ .fieldoffset = offsetoflow32(CPUARMState, cp15.vmpidr_el2) },
{ .name = "VMPIDR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 0, .crm = 0, .opc2 = 5,
.access = PL2_RW,
--
2.16.1
- [Qemu-devel] [PULL 00/32] target-arm queue, Peter Maydell, 2018/02/22
- [Qemu-devel] [PULL 03/32] hw/char/stm32f2xx_usart: fix TXE/TC bit handling, Peter Maydell, 2018/02/22
- [Qemu-devel] [PULL 04/32] Fix ast2500 protection register emulation, Peter Maydell, 2018/02/22
- [Qemu-devel] [PULL 01/32] target/arm: Fix register definitions for VMIDR and VMPIDR,
Peter Maydell <=
- [Qemu-devel] [PULL 05/32] hw/sd/milkymist-memcard: use qemu_log_mask(), Peter Maydell, 2018/02/22
- [Qemu-devel] [PULL 06/32] hw/sd/milkymist-memcard: split realize() out of SysBusDevice init(), Peter Maydell, 2018/02/22
- [Qemu-devel] [PULL 02/32] raspi: Add "raspi3" machine type, Peter Maydell, 2018/02/22
- [Qemu-devel] [PULL 08/32] hw/sd/ssi-sd: use the SDBus API, connect the SDCard to the bus, Peter Maydell, 2018/02/22
- [Qemu-devel] [PULL 10/32] sdcard: replace DPRINTF() by trace events, Peter Maydell, 2018/02/22
- [Qemu-devel] [PULL 07/32] hw/sd/milkymist-memcard: expose a SDBus and connect the SDCard to it, Peter Maydell, 2018/02/22
- [Qemu-devel] [PULL 09/32] sdcard: reorder SDState struct members, Peter Maydell, 2018/02/22
- [Qemu-devel] [PULL 11/32] sdcard: add a trace event for command responses, Peter Maydell, 2018/02/22
- [Qemu-devel] [PULL 13/32] sdcard: add more trace events, Peter Maydell, 2018/02/22
- [Qemu-devel] [PULL 12/32] sdcard: replace fprintf() by qemu_hexdump(), Peter Maydell, 2018/02/22