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From: | Richard Henderson |
Subject: | Re: [Qemu-devel] [PATCH v3 21/31] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16 |
Date: | Fri, 23 Feb 2018 16:28:59 -0800 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 02/23/2018 07:36 AM, Alex Bennée wrote: > Neither of these operations alter the floating point status registers > so we can do a pure bitwise operation, either squashing any sign > bit (ABS) or inverting it (NEG). > > Signed-off-by: Alex Bennée <address@hidden> > > --- > v3 > - fixup re-base conflicts > - make both operations pure bitwise TCG > --- > target/arm/translate-a64.c | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson <address@hidden> r~
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