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Re: [Qemu-devel] [PATCH v6 03/23] RISC-V CPU Core Definition
From: |
Igor Mammedov |
Subject: |
Re: [Qemu-devel] [PATCH v6 03/23] RISC-V CPU Core Definition |
Date: |
Mon, 26 Feb 2018 16:52:37 +0100 |
On Fri, 23 Feb 2018 13:11:49 +1300
Michael Clark <address@hidden> wrote:
> Add CPU state header, CPU definitions and initialization routines
>
> Reviewed-by: Richard Henderson <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
> ---
> target/riscv/cpu.c | 391 +++++++++++++++++++++++++++++++++++++++++++++
> target/riscv/cpu.h | 256 +++++++++++++++++++++++++++++
> target/riscv/cpu_bits.h | 416
> ++++++++++++++++++++++++++++++++++++++++++++++++
> 3 files changed, 1063 insertions(+)
> create mode 100644 target/riscv/cpu.c
> create mode 100644 target/riscv/cpu.h
> create mode 100644 target/riscv/cpu_bits.h
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
[...]
> +
> +static const RISCVCPUInfo riscv_cpus[] = {
> + { TYPE_RISCV_CPU_ANY, riscv_any_cpu_init },
> + { TYPE_RISCV_CPU_IMAFDCSU_PRIV_1_09, riscv_imafdcsu_priv1_9_cpu_init },
> + { TYPE_RISCV_CPU_IMAFDCSU_PRIV_1_10, riscv_imafdcsu_priv1_10_cpu_init },
> + { TYPE_RISCV_CPU_IMACU_PRIV_1_10, riscv_imacu_priv1_10_cpu_init },
> + { TYPE_RISCV_CPU_IMAC_PRIV_1_10, riscv_imac_priv1_10_cpu_init },
> + { NULL, NULL }
> +};
[...]
> +static void cpu_register(const RISCVCPUInfo *info)
> +{
> + TypeInfo type_info = {
> + .name = info->name,
> + .parent = TYPE_RISCV_CPU,
> + .instance_size = sizeof(RISCVCPU),
> + .instance_init = info->initfn,
> + };
> +
> + type_register(&type_info);
> +}
[...]
> +
> +void riscv_cpu_list(FILE *f, fprintf_function cpu_fprintf)
> +{
> + const RISCVCPUInfo *info = riscv_cpus;
> +
> + while (info->name) {
> + (*cpu_fprintf)(f, "%s\n", info->name);
> + info++;
> + }
> +}
majority targets use object_class_get_list() to get
the list of CPU types, you can use cris_cpu_list() as example.
> +static void riscv_cpu_register_types(void)
> +{
> + const RISCVCPUInfo *info = riscv_cpus;
> +
> + type_register_static(&riscv_cpu_type_info);
> +
> + while (info->name) {
> + cpu_register(info);
> + info++;
> + }
> +}
> +
> +type_init(riscv_cpu_register_types)
[...]
This still hasn't addressed a comment from
"[PATCH v4 03/22] RISC-V CPU Core Definition"
and uses old approach with RISCVCPUInfo helper structure.
Please, use commit 974e58d2 to model after.
- [Qemu-devel] [PATCH v6 00/23] RISC-V QEMU Port Submission, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 02/23] RISC-V ELF Machine Definition, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 01/23] RISC-V Maintainers, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 03/23] RISC-V CPU Core Definition, Michael Clark, 2018/02/22
- Re: [Qemu-devel] [PATCH v6 03/23] RISC-V CPU Core Definition,
Igor Mammedov <=
- [Qemu-devel] [PATCH v6 06/23] RISC-V FPU Support, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 09/23] RISC-V Physical Memory Protection, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 07/23] RISC-V GDB Stub, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 19/23] SiFive RISC-V PRCI Block, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 11/23] Add symbol table callback function interface to load_elf, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 08/23] RISC-V TCG Code Generation, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 10/23] RISC-V Linux User Emulation, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 05/23] RISC-V CPU Helpers, Michael Clark, 2018/02/22
- [Qemu-devel] [PATCH v6 13/23] RISC-V HART Array, Michael Clark, 2018/02/22