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Re: [Qemu-devel] [PATCH v4 14/31] arm/translate-a64: add FP16 FMULX/MLS/
From: |
Alex Bennée |
Subject: |
Re: [Qemu-devel] [PATCH v4 14/31] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed |
Date: |
Tue, 27 Feb 2018 17:52:10 +0000 |
User-agent: |
mu4e 1.1.0; emacs 26.0.91 |
Richard Henderson <address@hidden> writes:
> On 02/27/2018 06:38 AM, Alex Bennée wrote:
>> @@ -11244,7 +11245,7 @@ static void disas_simd_indexed(DisasContext *s,
>> uint32_t insn)
>> }
>> /* fall through */
>> case 0x9: /* FMUL, FMULX */
>> - if (!extract32(size, 1, 1)) {
>> + if (size == 1) {
>> unallocated_encoding(s);
>> return;
>> }
>
> This is still redundant, since size == 1 is handled...
doh!
will fix.
>
>> @@ -11256,18 +11257,34 @@ static void disas_simd_indexed(DisasContext *s,
>> uint32_t insn)
>> }
>>
>> if (is_fp) {
>> - /* low bit of size indicates single/double */
>> - size = extract32(size, 0, 1) ? 3 : 2;
>> - if (size == 2) {
>> + /* convert insn encoded size to TCGMemOp size */
>> + switch (size) {
>> + case 2: /* single precision */
>> + size = MO_32;
>> index = h << 1 | l;
>> - } else {
>> + rm |= (m << 4);
>> + break;
>> + case 3: /* double precision */
>> + size = MO_64;
>> if (l || !is_q) {
>> unallocated_encoding(s);
>> return;
>> }
>> index = h;
>> + rm |= (m << 4);
>> + break;
>> + case 0: /* half precision */
>> + size = MO_16;
>> + index = h << 2 | l << 1 | m;
>> + is_fp16 = true;
>> + if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
>> + break;
>> + }
>> + /* fallthru */
>> + default: /* unallocated */
>> + unallocated_encoding(s);
>> + return;
>> }
>
> ... here. But it's not wrong and I can clean this up along with the
> additional
> changes I need to make to this function for fcmla support. So,
>
> Reviewed-by: Richard Henderson <address@hidden>
>
>
> r~
--
Alex Bennée
- [Qemu-devel] [PATCH v4 23/31] arm/translate-a64: add FP16 FRECPE, (continued)
- [Qemu-devel] [PATCH v4 23/31] arm/translate-a64: add FP16 FRECPE, Alex Bennée, 2018/02/27
- [Qemu-devel] [PATCH v4 11/31] arm/translate-a64: add FP16 FMULA/X/S to simd_three_reg_same_fp16, Alex Bennée, 2018/02/27
- [Qemu-devel] [PATCH v4 19/31] arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/27
- [Qemu-devel] [PATCH v4 24/31] arm/translate-a64: add FP16 FRCPX to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/27
- [Qemu-devel] [PATCH v4 30/31] arm/translate-a64: implement simd_scalar_three_reg_same_fp16, Alex Bennée, 2018/02/27
- [Qemu-devel] [PATCH v4 31/31] arm/translate-a64: add all single op FP16 to handle_fp_1src_half, Alex Bennée, 2018/02/27
- [Qemu-devel] [PATCH v4 29/31] arm/translate-a64: add all FP16 ops in simd_scalar_pairwise, Alex Bennée, 2018/02/27
- [Qemu-devel] [PATCH v4 13/31] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16, Alex Bennée, 2018/02/27
- [Qemu-devel] [PATCH v4 14/31] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed, Alex Bennée, 2018/02/27
[Qemu-devel] [PATCH v4 27/31] arm/translate-a64: add FP16 FRSQRTE to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/27
[Qemu-devel] [PATCH v4 20/31] arm/translate-a64: add FP16 SCVTF/UCVFT to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/27
[Qemu-devel] [PATCH v4 26/31] arm/helper.c: re-factor rsqrte and add rsqrte_f16, Alex Bennée, 2018/02/27
[Qemu-devel] [PATCH v4 25/31] arm/translate-a64: add FP16 FSQRT to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/27
[Qemu-devel] [PATCH v4 21/31] arm/translate-a64: add FP16 FNEG/FABS to simd_two_reg_misc_fp16, Alex Bennée, 2018/02/27
[Qemu-devel] [PATCH v4 22/31] arm/helper.c: re-factor recpe and add recepe_f16, Alex Bennée, 2018/02/27
Re: [Qemu-devel] [PATCH v4 00/31] Add ARMv8.2 half-precision functions, no-reply, 2018/02/27
Re: [Qemu-devel] [PATCH v4 00/31] Add ARMv8.2 half-precision functions, no-reply, 2018/02/27