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[Qemu-devel] [PULL 03/42] xilinx_spips: Use 8 dummy cycles with the QIOR
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 03/42] xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands |
Date: |
Thu, 1 Mar 2018 11:23:24 +0000 |
From: Francisco Iglesias <address@hidden>
Use 8 dummy cycles (4 dummy bytes) with the QIOR/QIOR4 commands in legacy mode
for matching what is expected by Micron (Numonyx) flashes (the default target
flash type of the QSPI).
Signed-off-by: Francisco Iglesias <address@hidden>
Tested-by: Alistair Francis <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
hw/ssi/xilinx_spips.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c
index 0cb484ecf4..426f971311 100644
--- a/hw/ssi/xilinx_spips.c
+++ b/hw/ssi/xilinx_spips.c
@@ -577,7 +577,7 @@ static int xilinx_spips_num_dummies(XilinxQSPIPS *qs,
uint8_t command)
return 2;
case QIOR:
case QIOR_4:
- return 5;
+ return 4;
default:
return -1;
}
--
2.16.2
- [Qemu-devel] [PULL 04/42] i2c: Fix some brace style issues, (continued)
- [Qemu-devel] [PULL 04/42] i2c: Fix some brace style issues, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 14/42] arm/translate-a64: implement half-precision F(MIN|MAX)(V|NMV), Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 07/42] hw/sii9022: Add support for Silicon Image SII9022, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 16/42] arm/translate-a64: initial decode for simd_three_reg_same_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 18/42] arm/translate-a64: add FP16 F[A]C[EQ/GE/GT] to simd_three_reg_same_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 20/42] arm/translate-a64: add FP16 FR[ECP/SQRT]S to simd_three_reg_same_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 09/42] include/exec/helper-head.h: support f16 in helper calls, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 08/42] arm/vexpress: Add proper display connector emulation, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 06/42] hw/i2c-ddc: Do not fail writes, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 05/42] i2c: Move the bus class to i2c.h, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 03/42] xilinx_spips: Use 8 dummy cycles with the QIOR/QIOR4 commands,
Peter Maydell <=
- [Qemu-devel] [PULL 02/42] xilinx_spips: Enable only two slaves when reading/writing with stripe, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 17/42] arm/translate-a64: add FP16 FADD/FABD/FSUB/FMUL/FDIV to simd_three_reg_same_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 13/42] target/arm/helper: pass explicit fpst to set_rmode, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 21/42] arm/translate-a64: add FP16 pairwise ops simd_three_reg_same_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 24/42] arm/translate-a64: initial decode for simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 22/42] arm/translate-a64: add FP16 FMULX/MLS/FMLA to simd_indexed, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 25/42] arm/translate-a64: add FP16 FPRINTx to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 26/42] arm/translate-a64: add FCVTxx to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 27/42] arm/translate-a64: add FP16 FCMxx (zero) to simd_two_reg_misc_fp16, Peter Maydell, 2018/03/01
- [Qemu-devel] [PULL 31/42] arm/translate-a64: add FP16 FRECPE, Peter Maydell, 2018/03/01