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[Qemu-devel] [PULL 32/39] target/arm: Enable ARM_FEATURE_V8_RDM
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 32/39] target/arm: Enable ARM_FEATURE_V8_RDM |
Date: |
Fri, 2 Mar 2018 11:06:33 +0000 |
From: Richard Henderson <address@hidden>
Enable it for the "any" CPU used by *-linux-user.
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/cpu.c | 1 +
target/arm/cpu64.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index e08b1e7943..3ee2d32aef 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1697,6 +1697,7 @@ static void arm_any_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
set_feature(&cpu->env, ARM_FEATURE_CRC);
+ set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
cpu->midr = 0xffffffff;
}
#endif
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 9743bdc8c3..7246866e7d 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -230,6 +230,7 @@ static void aarch64_any_initfn(Object *obj)
set_feature(&cpu->env, ARM_FEATURE_V8_SM4);
set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
set_feature(&cpu->env, ARM_FEATURE_CRC);
+ set_feature(&cpu->env, ARM_FEATURE_V8_RDM);
set_feature(&cpu->env, ARM_FEATURE_V8_FP16);
cpu->ctr = 0x80038003; /* 32 byte I and D cacheline size, VIPT icache */
cpu->dcz_blocksize = 7; /* 512 bytes */
--
2.16.2
- [Qemu-devel] [PULL 26/39] target/arm: Refactor disas_simd_indexed size checks, (continued)
- [Qemu-devel] [PULL 26/39] target/arm: Refactor disas_simd_indexed size checks, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 25/39] target/arm: Refactor disas_simd_indexed decode, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 18/39] hw/misc/tz-ppc: Model TrustZone peripheral protection controller, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 28/39] target/arm: Decode aa64 armv8.1 three same extra, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 22/39] hw/arm/iotkit: Model Arm IOT Kit, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 34/39] target/arm: Decode aa64 armv8.3 fcadd, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 39/39] target/arm: Enable ARM_FEATURE_V8_FCMA, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 29/39] target/arm: Decode aa64 armv8.1 scalar/vector x indexed element, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 23/39] mps2-an505: New board model: MPS2 with AN505 Cortex-M33 FPGA image, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 27/39] target/arm: Decode aa64 armv8.1 scalar three same extra, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 32/39] target/arm: Enable ARM_FEATURE_V8_RDM,
Peter Maydell <=
- [Qemu-devel] [PULL 31/39] target/arm: Decode aa32 armv8.1 two reg and a scalar, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 35/39] target/arm: Decode aa64 armv8.3 fcmla, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 30/39] target/arm: Decode aa32 armv8.1 three same, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 36/39] target/arm: Decode aa32 armv8.3 3-same, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 38/39] target/arm: Decode t32 simd 3reg and 2reg_scalar extension, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 37/39] target/arm: Decode aa32 armv8.3 2-reg-index, Peter Maydell, 2018/03/02
- [Qemu-devel] [PULL 33/39] target/arm: Add ARM_FEATURE_V8_FCMA, Peter Maydell, 2018/03/02
- Re: [Qemu-devel] [PULL 00/39] target-arm queue, no-reply, 2018/03/02
- Re: [Qemu-devel] [PULL 00/39] target-arm queue, Peter Maydell, 2018/03/02