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[Qemu-devel] [PATCH v1 17/22] RISC-V: Hardwire satp to 0 for no-mmu case
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v1 17/22] RISC-V: Hardwire satp to 0 for no-mmu case |
Date: |
Wed, 7 Mar 2018 09:56:25 +1300 |
satp is WARL so it should not trap on illegal writes, rather
it can be hardwired to zero and silently ignore illegal writes.
It seems the RISC-V WARL behaviour is preferred to having to
bear trap overhead, versus simply reading back the value and
checking if the write took (saves hundreds of cycles and much
more complex trap handling code).
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/op_helper.c | 7 +++++--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
index e34715d..dd3e417 100644
--- a/target/riscv/op_helper.c
+++ b/target/riscv/op_helper.c
@@ -242,7 +242,7 @@ void csr_write_helper(CPURISCVState *env, target_ulong
val_to_write,
}
case CSR_SATP: /* CSR_SPTBR */ {
if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
- goto do_illegal;
+ break;
}
if (env->priv_ver <= PRIV_VERSION_1_09_1 && (val_to_write ^
env->sptbr))
{
@@ -452,7 +452,10 @@ target_ulong csr_read_helper(CPURISCVState *env,
target_ulong csrno)
return env->scounteren;
case CSR_SCAUSE:
return env->scause;
- case CSR_SPTBR:
+ case CSR_SATP: /* CSR_SPTBR */
+ if (!riscv_feature(env, RISCV_FEATURE_MMU)) {
+ return 0;
+ }
if (env->priv_ver >= PRIV_VERSION_1_10_0) {
return env->satp;
} else {
--
2.7.0
- [Qemu-devel] [PATCH v1 06/22] RISC-V: Mark ROM read-only after copying in code, (continued)
- [Qemu-devel] [PATCH v1 06/22] RISC-V: Mark ROM read-only after copying in code, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 07/22] RISC-V: Remove unused class definitions, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 08/22] RISC-V: Make sure rom has space for fdt, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 09/22] RISC-V: Include hexidecimal in disassembly, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 10/22] RISC-V: Hold rcu_read_lock when accessing memory, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 11/22] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 12/22] RISC-V: Update E order and I extension order, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 14/22] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 13/22] RISC-V: Make some header guards more specific, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 15/22] RISC-V: Use memory_region_is_ram in pte update, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 17/22] RISC-V: Hardwire satp to 0 for no-mmu case,
Michael Clark <=
- [Qemu-devel] [PATCH v1 16/22] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 18/22] RISC-V: Remove braces from satp case statement, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 19/22] RISC-V: riscv-qemu port supports sv39 and sv48, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 20/22] RISC-V: vectored traps are optional, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 21/22] RISC-V: No traps on writes to misa/minstret/mcycle, Michael Clark, 2018/03/06
- [Qemu-devel] [PATCH v1 22/22] RISC-V: Remove support for adhoc X_COP interrupt, Michael Clark, 2018/03/06