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[Qemu-devel] [PATCH v3 10/24] RISC-V: Hold rcu_read_lock when accessing
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v3 10/24] RISC-V: Hold rcu_read_lock when accessing memory |
Date: |
Fri, 16 Mar 2018 12:41:07 -0700 |
>From reading other code that accesses memory regions directly,
it appears that the rcu_read_lock needs to be held. Note: the
original code for accessing RAM directly was added because
there is no other way to use atomic_cmpxchg on guest physical
address space.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/helper.c | 14 ++++++++++++--
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/target/riscv/helper.c b/target/riscv/helper.c
index 02cbcea..e71633a 100644
--- a/target/riscv/helper.c
+++ b/target/riscv/helper.c
@@ -209,6 +209,9 @@ restart:
as the PTE is no longer valid */
MemoryRegion *mr;
hwaddr l = sizeof(target_ulong), addr1;
+ enum { success, translate_fail, restart_walk} action = success;
+
+ rcu_read_lock();
mr = address_space_translate(cs->as, pte_addr,
&addr1, &l, false);
if (memory_access_is_direct(mr, true)) {
@@ -222,7 +225,7 @@ restart:
target_ulong old_pte =
atomic_cmpxchg(pte_pa, pte, updated_pte);
if (old_pte != pte) {
- goto restart;
+ action = restart_walk;
} else {
pte = updated_pte;
}
@@ -230,7 +233,14 @@ restart:
} else {
/* misconfigured PTE in ROM (AD bits are not preset) or
* PTE is in IO space and can't be updated atomically */
- return TRANSLATE_FAIL;
+ action = translate_fail;
+ }
+ rcu_read_unlock();
+
+ switch (action) {
+ case success: break;
+ case translate_fail: return TRANSLATE_FAIL;
+ case restart_walk: goto restart;
}
}
--
2.7.0
- [Qemu-devel] [PATCH v3 00/24] RISC-V Post-merge spec conformance and cleanup, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 03/24] RISC-V: Make virt board description match spike, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 01/24] RISC-V: Make virt create_fdt interface consistent, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 04/24] RISC-V: Use ROM base address and size from memmap, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 02/24] RISC-V: Replace hardcoded constants with enum values, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 05/24] RISC-V: Remove identity_translate from load_elf, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 06/24] RISC-V: Mark ROM read-only after copying in code, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 07/24] RISC-V: Remove unused class definitions, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 08/24] RISC-V: Make sure rom has space for fdt, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 09/24] RISC-V: Include intruction hex in disassembly, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 10/24] RISC-V: Hold rcu_read_lock when accessing memory,
Michael Clark <=
[Qemu-devel] [PATCH v3 13/24] RISC-V: Make some header guards more specific, Michael Clark, 2018/03/16
[Qemu-devel] [PATCH v3 12/24] RISC-V: Update E order and I extension order, Michael Clark, 2018/03/16
[Qemu-devel] [PATCH v3 11/24] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/03/16
[Qemu-devel] [PATCH v3 14/24] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/03/16
[Qemu-devel] [PATCH v3 15/24] RISC-V: Use memory_region_is_ram in pte update, Michael Clark, 2018/03/16
[Qemu-devel] [PATCH v3 16/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/03/16