[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v3 24/24] RISC-V: Clear mtval/stval on exceptions wi
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PATCH v3 24/24] RISC-V: Clear mtval/stval on exceptions without info |
Date: |
Fri, 16 Mar 2018 12:41:21 -0700 |
mtval/stval must be set on all exceptions but zero is
a legal value if there is no exception specific info.
Placing the instruction bytes for illegal instruction
exceptions in mtval/stval is an optional feature and
is currently not supported by QEMU RISC-V.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
---
target/riscv/helper.c | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/target/riscv/helper.c b/target/riscv/helper.c
index c430e95..54d4ff7 100644
--- a/target/riscv/helper.c
+++ b/target/riscv/helper.c
@@ -499,6 +499,10 @@ void riscv_cpu_do_interrupt(CPUState *cs)
": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr);
}
env->sbadaddr = env->badaddr;
+ } else {
+ /* otherwise we must clear sbadaddr/stval
+ * todo: support populating stval on illegal instructions */
+ env->sbadaddr = 0;
}
target_ulong s = env->mstatus;
@@ -520,6 +524,10 @@ void riscv_cpu_do_interrupt(CPUState *cs)
": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr);
}
env->mbadaddr = env->badaddr;
+ } else {
+ /* otherwise we must clear mbadaddr/mtval
+ * todo: support populating mtval on illegal instructions */
+ env->mbadaddr = 0;
}
target_ulong s = env->mstatus;
--
2.7.0
- [Qemu-devel] [PATCH v3 11/24] RISC-V: Improve page table walker spec compliance, (continued)
- [Qemu-devel] [PATCH v3 11/24] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 14/24] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 15/24] RISC-V: Use memory_region_is_ram in pte update, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 16/24] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 18/24] RISC-V: Remove braces from satp case statement, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 17/24] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 19/24] RISC-V: riscv-qemu port supports sv39 and sv48, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 20/24] RISC-V: vectored traps are optional, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 22/24] RISC-V: Remove support for adhoc X_COP interrupt, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 21/24] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/03/16
- [Qemu-devel] [PATCH v3 24/24] RISC-V: Clear mtval/stval on exceptions without info,
Michael Clark <=
- [Qemu-devel] [PATCH v3 23/24] RISC-V: Convert cpu definition towards future model, Michael Clark, 2018/03/16
- Re: [Qemu-devel] [PATCH v3 00/24] RISC-V Post-merge spec conformance and cleanup, no-reply, 2018/03/16