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[Qemu-devel] [PULL 14/24] RISC-V: Use memory_region_is_ram in pte update
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PULL 14/24] RISC-V: Use memory_region_is_ram in pte update |
Date: |
Wed, 21 Mar 2018 13:46:50 -0700 |
After reading cpu_physical_memory_write and friends, it seems
that memory_region_is_ram is a more appropriate interface,
and matches the intent of the code that is calling it.
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/helper.c b/target/riscv/helper.c
index 9010620..b2e3f45 100644
--- a/target/riscv/helper.c
+++ b/target/riscv/helper.c
@@ -234,7 +234,7 @@ restart:
hwaddr l = sizeof(target_ulong), addr1;
mr = address_space_translate(cs->as, pte_addr,
&addr1, &l, false);
- if (memory_access_is_direct(mr, true)) {
+ if (memory_region_is_ram(mr)) {
target_ulong *pte_pa =
qemu_map_ram_ptr(mr->ram_block, addr1);
#if TCG_OVERSIZED_GUEST
--
2.7.0
- [Qemu-devel] [PULL 00/24] RISC-V: Post-merge spec conformance and cleanup v5, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 04/24] RISC-V: Use ROM base address and size from memmap, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 01/24] RISC-V: Make virt create_fdt interface consistent, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 03/24] RISC-V: Make virt board description match spike, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 02/24] RISC-V: Replace hardcoded constants with enum values, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 07/24] RISC-V: Remove unused class definitions, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 06/24] RISC-V: Mark ROM read-only after copying in code, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 05/24] RISC-V: Remove identity_translate from load_elf, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 14/24] RISC-V: Use memory_region_is_ram in pte update,
Michael Clark <=
- [Qemu-devel] [PULL 11/24] RISC-V: Update E order and I extension order, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 17/24] RISC-V: Remove braces from satp case statement, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 18/24] RISC-V: riscv-qemu port supports sv39 and sv48, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 20/24] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 19/24] RISC-V: vectored traps are optional, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 09/24] RISC-V: Include intruction hex in disassembly, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 08/24] RISC-V: Make sure rom has space for fdt, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 10/24] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 13/24] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/03/21
- [Qemu-devel] [PULL 12/24] RISC-V: Make some header guards more specific, Michael Clark, 2018/03/21