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Re: [Qemu-devel] [PATCH v1 2/2] RISC-V: Fix incorrect disassembly for ad
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From: |
Richard Henderson |
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Subject: |
Re: [Qemu-devel] [PATCH v1 2/2] RISC-V: Fix incorrect disassembly for addiw |
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Date: |
Wed, 28 Mar 2018 12:40:23 +0800 |
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User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 |
On 03/28/2018 03:55 AM, Michael Clark wrote:
> This fixes a bug in the disassembler constraints used
> to lift instructions into pseudo-instructions, whereby
> addiw instructions are always lifted to sext.w instead
> of just lifting addiw with a zero immediate.
>
> An associated fix has been made to the metadata used to
> machine generate the disseasembler:
>
> https://github.com/michaeljclark/riscv-meta/
> commit/4a6b2f3898430768acfe201405224d2ea31e1477
>
> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Cc: Palmer Dabbelt <address@hidden>
> Cc: Peter Maydell <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
> ---
> disas/riscv.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson <address@hidden>
r~