[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH v6 7/9] i386: Add support for CPUID_8000_001E for AM
From: |
Babu Moger |
Subject: |
[Qemu-devel] [PATCH v6 7/9] i386: Add support for CPUID_8000_001E for AMD |
Date: |
Tue, 10 Apr 2018 19:16:07 -0400 |
Populate threads/core_id/apic_ids/socket_id when CPUID_EXT3_TOPOEXT
feature is supported. This is required to support hyperthreading feature
on AMD CPUs. This is supported via CPUID_8000_001E extended functions.
Signed-off-by: Babu Moger <address@hidden>
Tested-by: Geoffrey McRae <address@hidden>
---
target/i386/cpu.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 63f2d31..24b39c6 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -315,6 +315,12 @@ static uint32_t encode_cache_cpuid80000005(CPUCacheInfo
*cache)
(((CORES_IN_CMPLX - 1) * 2) + 1) : \
(CORES_IN_CMPLX - 1))
+/* Definitions used on CPUID Leaf 0x8000001E */
+#define EXTENDED_APIC_ID(threads, socket_id, core_id, thread_id) \
+ ((threads) ? \
+ ((socket_id << 6) | (core_id << 1) | thread_id) : \
+ ((socket_id << 6) | core_id))
+
/*
* Encode cache info for CPUID[0x80000006].ECX and CPUID[0x80000006].EDX
* @l3 can be NULL.
@@ -4098,6 +4104,14 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,
uint32_t count,
break;
}
break;
+ case 0x8000001E:
+ assert(cpu->core_id <= 255);
+ *eax = EXTENDED_APIC_ID((cs->nr_threads - 1),
+ cpu->socket_id, cpu->core_id, cpu->thread_id);
+ *ebx = (cs->nr_threads - 1) << 8 | cpu->core_id;
+ *ecx = cpu->socket_id;
+ *edx = 0;
+ break;
case 0xC0000000:
*eax = env->cpuid_xlevel2;
*ebx = 0;
--
1.8.3.1
- [Qemu-devel] [PATCH v6 0/9] i386: Enable TOPOEXT to support hyperthreading on AMD CPU, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 2/9] i386: Add cache information in X86CPUDefinition, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 1/9] i386: Helpers to encode cache information consistently, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 4/9] i386: Add new property to control cache info, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 3/9] i386: Initialize cache information for EPYC family processors, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 5/9] i386: Use the statically loaded cache definitions, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 6/9] i386: Populate AMD Processor Cache Information for cpuid 0x8000001D, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 8/9] i386: Enable TOPOEXT feature on AMD EPYC CPU, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 9/9] i386: Remove generic SMT thread check, Babu Moger, 2018/04/10
- [Qemu-devel] [PATCH v6 7/9] i386: Add support for CPUID_8000_001E for AMD,
Babu Moger <=