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Re: [Qemu-devel] [PATCH v8 10/35] RISC-V: Remove erroneous comment from
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH v8 10/35] RISC-V: Remove erroneous comment from translate.c |
Date: |
Thu, 26 Apr 2018 16:48:49 +0000 |
On Wed, Apr 25, 2018 at 5:00 PM Michael Clark <address@hidden> wrote:
> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Cc: Palmer Dabbelt <address@hidden>
> Cc: Alistair Francis <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Alistair
> ---
> target/riscv/translate.c | 1 -
> 1 file changed, 1 deletion(-)
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 808eab7..c3a029a 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -280,7 +280,6 @@ static void gen_arith(DisasContext *ctx, uint32_t
opc, int rd, int rs1,
> tcg_gen_andi_tl(source2, source2, 0x1F);
> tcg_gen_sar_tl(source1, source1, source2);
> break;
> - /* fall through to SRA */
> #endif
> case OPC_RISC_SRA:
> tcg_gen_andi_tl(source2, source2, TARGET_LONG_BITS - 1);
> --
> 2.7.0
- [Qemu-devel] [PATCH v8 06/35] RISC-V: Include instruction hex in disassembly, (continued)
- [Qemu-devel] [PATCH v8 06/35] RISC-V: Include instruction hex in disassembly, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 07/35] RISC-V: Make some header guards more specific, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 08/35] RISC-V: Make virt header comment title consistent, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 09/35] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 10/35] RISC-V: Remove erroneous comment from translate.c, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 12/35] RISC-V: Update address bits to support sv39 and sv48, Michael Clark, 2018/04/25
- [Qemu-devel] [PATCH v8 11/35] RISC-V: Mark ROM read-only after copying in code, Michael Clark, 2018/04/25
[Qemu-devel] [PATCH v8 13/35] RISC-V: Improve page table walker spec compliance, Michael Clark, 2018/04/25
[Qemu-devel] [PATCH v8 14/35] RISC-V: Update E order and I extension order, Michael Clark, 2018/04/25
[Qemu-devel] [PATCH v8 15/35] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/04/25