[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 09/20] RISC-V: Make virt header comment title consist
From: |
Michael Clark |
Subject: |
[Qemu-devel] [PULL 09/20] RISC-V: Make virt header comment title consistent |
Date: |
Sun, 6 May 2018 11:35:14 +1200 |
Cc: Sagar Karandikar <address@hidden>
Cc: Bastian Koppelmann <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
include/hw/riscv/virt.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 3a4f23e8d075..91163d6cbfe8 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -1,5 +1,5 @@
/*
- * SiFive VirtIO Board
+ * QEMU RISC-V VirtIO machine interface
*
* Copyright (c) 2017 SiFive, Inc.
*
--
2.7.0
- [Qemu-devel] [PULL 00/20] RISC-V: QEMU 2.13 Privileged ISA emulation updates, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 01/20] RISC-V: Replace hardcoded constants with enum values, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 02/20] RISC-V: Make virt board description match spike, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 03/20] RISC-V: Use ROM base address and size from memmap, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 04/20] RISC-V: Remove identity_translate from load_elf, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 05/20] RISC-V: Remove unused class definitions, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 06/20] RISC-V: Include instruction hex in disassembly, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 07/20] RISC-V: Fix missing break statement in disassembler, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 08/20] RISC-V: Make some header guards more specific, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 09/20] RISC-V: Make virt header comment title consistent,
Michael Clark <=
- [Qemu-devel] [PULL 11/20] RISC-V: Remove erroneous comment from translate.c, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 10/20] RISC-V: Remove EM_RISCV ELF_MACHINE indirection, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 12/20] RISC-V: Update E and I extension order, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 13/20] RISC-V: Hardwire satp to 0 for no-mmu case, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 14/20] RISC-V: Clear mtval/stval on exceptions without info, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 15/20] RISC-V: Allow S-mode mxr access when priv ISA >= v1.10, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 16/20] RISC-V: Use [ms]counteren CSRs when priv ISA >= v1.10, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 17/20] RISC-V: Add mcycle/minstret support for -icount auto, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 18/20] RISC-V: Make mtvec/stvec ignore vectored traps, Michael Clark, 2018/05/05
- [Qemu-devel] [PULL 19/20] RISC-V: No traps on writes to misa, minstret, mcycle, Michael Clark, 2018/05/05