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[Qemu-devel] [PATCH v3 0/7] RISC-V: SoCify SiFive boards and connect GEM
From: |
Alistair Francis |
Subject: |
[Qemu-devel] [PATCH v3 0/7] RISC-V: SoCify SiFive boards and connect GEM |
Date: |
Mon, 14 May 2018 17:06:36 -0700 |
This series has three tasks:
1. To convert the SiFive U and E machines into SoCs and boards
2. To connect the Cadence GEM device to the SiFive U board
3. Fix some device tree problems with the SiFive U board
After this series the SiFive E and U boards have their SoCs split into
seperate QEMU objects, which can be used on future boards if desired.
The RISC-V Virt and Spike boards have not been converted. They haven't
been converted as they aren't physical boards, so it doesn't make a
whole lot of sense to split them into an SoC and board. The only
disadvantage with this is that they now differ to the SiFive boards.
This series also connect the Cadence GEM device to the SiFive U board.
There are some interrupt line changes requried before this is possible.
V3:
- Generalise the SoC names
V2:
- Use the new GPIOs everywhere in the board
- Add the GEM device tree node
- Fix some device tree problems identified
Alistair Francis (7):
hw/riscv/sifive_u: Create a SiFive U SoC object
hw/riscv/sifive_e: Create a SiFive E SoC object
hw/riscv/sifive_plic: Use gpios instead of irqs
hw/riscv/sifive_u: Set the soc device tree node as a simple-bus
hw/riscv/sifive_u: Set the interrupt controler number of interrupts
hw/riscv/sifive_u: Move the uart device tree node under /soc/
hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device
default-configs/riscv32-softmmu.mak | 1 +
default-configs/riscv64-softmmu.mak | 1 +
hw/riscv/sifive_e.c | 102 ++++++++++++++-----
hw/riscv/sifive_plic.c | 6 +-
hw/riscv/sifive_u.c | 151 +++++++++++++++++++++++-----
hw/riscv/virt.c | 4 +-
include/hw/riscv/sifive_e.h | 16 ++-
include/hw/riscv/sifive_plic.h | 1 -
include/hw/riscv/sifive_u.h | 25 ++++-
9 files changed, 239 insertions(+), 68 deletions(-)
--
2.17.0
- [Qemu-devel] [PATCH v3 0/7] RISC-V: SoCify SiFive boards and connect GEM,
Alistair Francis <=
- [Qemu-devel] [PATCH v3 1/7] hw/riscv/sifive_u: Create a SiFive U SoC object, Alistair Francis, 2018/05/14
- [Qemu-devel] [PATCH v3 2/7] hw/riscv/sifive_e: Create a SiFive E SoC object, Alistair Francis, 2018/05/14
- [Qemu-devel] [PATCH v3 3/7] hw/riscv/sifive_plic: Use gpios instead of irqs, Alistair Francis, 2018/05/14
- [Qemu-devel] [PATCH v3 4/7] hw/riscv/sifive_u: Set the soc device tree node as a simple-bus, Alistair Francis, 2018/05/14
- [Qemu-devel] [PATCH v3 5/7] hw/riscv/sifive_u: Set the interrupt controler number of interrupts, Alistair Francis, 2018/05/14
- [Qemu-devel] [PATCH v3 6/7] hw/riscv/sifive_u: Move the uart device tree node under /soc/, Alistair Francis, 2018/05/14
- [Qemu-devel] [PATCH v3 7/7] hw/riscv/sifive_u: Connect the Cadence GEM Ethernet device, Alistair Francis, 2018/05/14