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Re: [Qemu-devel] [PATCH v5 20/28] fpu/softfloat: Use float*_silence_nan
From: |
Alex Bennée |
Subject: |
Re: [Qemu-devel] [PATCH v5 20/28] fpu/softfloat: Use float*_silence_nan in propagateFloat*NaN |
Date: |
Tue, 15 May 2018 14:40:25 +0100 |
User-agent: |
mu4e 1.1.0; emacs 26.1 |
Richard Henderson <address@hidden> writes:
> We have already checked the arguments for SNaN;
> we don't need to do it again.
>
> Reviewed-by: Peter Maydell <address@hidden>
> Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Alex Bennée <address@hidden>
> ---
> fpu/softfloat-specialize.h | 44 +++++++++++++++++++++++++++++---------
> 1 file changed, 34 insertions(+), 10 deletions(-)
>
> diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat-specialize.h
> index 995a0132c6..4fa068a5dc 100644
> --- a/fpu/softfloat-specialize.h
> +++ b/fpu/softfloat-specialize.h
> @@ -498,7 +498,7 @@ static float32 commonNaNToFloat32(commonNaNT a,
> float_status *status)
> | The routine is passed various bits of information about the
> | two NaNs and should return 0 to select NaN a and 1 for NaN b.
> | Note that signalling NaNs are always squashed to quiet NaNs
> -| by the caller, by calling floatXX_maybe_silence_nan() before
> +| by the caller, by calling floatXX_silence_nan() before
> | returning them.
> |
> | aIsLargerSignificand is only valid if both a and b are NaNs
> @@ -536,7 +536,7 @@ static int pickNaN(flag aIsQNaN, flag aIsSNaN, flag
> bIsQNaN, flag bIsSNaN,
> {
> /* According to MIPS specifications, if one of the two operands is
> * a sNaN, a new qNaN has to be generated. This is done in
> - * floatXX_maybe_silence_nan(). For qNaN inputs the specifications
> + * floatXX_silence_nan(). For qNaN inputs the specifications
> * says: "When possible, this QNaN result is one of the operand QNaN
> * values." In practice it seems that most implementations choose
> * the first operand if both operands are qNaN. In short this gives
> @@ -788,9 +788,15 @@ static float32 propagateFloat32NaN(float32 a, float32 b,
> float_status *status)
>
> if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
> aIsLargerSignificand)) {
> - return float32_maybe_silence_nan(b, status);
> + if (bIsSignalingNaN) {
> + return float32_silence_nan(b, status);
> + }
> + return b;
> } else {
> - return float32_maybe_silence_nan(a, status);
> + if (aIsSignalingNaN) {
> + return float32_silence_nan(a, status);
> + }
> + return a;
> }
> }
>
> @@ -950,9 +956,15 @@ static float64 propagateFloat64NaN(float64 a, float64 b,
> float_status *status)
>
> if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
> aIsLargerSignificand)) {
> - return float64_maybe_silence_nan(b, status);
> + if (bIsSignalingNaN) {
> + return float64_silence_nan(b, status);
> + }
> + return b;
> } else {
> - return float64_maybe_silence_nan(a, status);
> + if (aIsSignalingNaN) {
> + return float64_silence_nan(a, status);
> + }
> + return a;
> }
> }
>
> @@ -1121,9 +1133,15 @@ floatx80 propagateFloatx80NaN(floatx80 a, floatx80 b,
> float_status *status)
>
> if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
> aIsLargerSignificand)) {
> - return floatx80_maybe_silence_nan(b, status);
> + if (bIsSignalingNaN) {
> + return floatx80_silence_nan(b, status);
> + }
> + return b;
> } else {
> - return floatx80_maybe_silence_nan(a, status);
> + if (aIsSignalingNaN) {
> + return floatx80_silence_nan(a, status);
> + }
> + return a;
> }
> }
>
> @@ -1270,8 +1288,14 @@ static float128 propagateFloat128NaN(float128 a,
> float128 b,
>
> if (pickNaN(aIsQuietNaN, aIsSignalingNaN, bIsQuietNaN, bIsSignalingNaN,
> aIsLargerSignificand)) {
> - return float128_maybe_silence_nan(b, status);
> + if (bIsSignalingNaN) {
> + return float128_silence_nan(b, status);
> + }
> + return b;
> } else {
> - return float128_maybe_silence_nan(a, status);
> + if (aIsSignalingNaN) {
> + return float128_silence_nan(a, status);
> + }
> + return a;
> }
> }
--
Alex Bennée
- Re: [Qemu-devel] [PATCH v5 13/28] fpu/softfloat: Partial support for ARM Alternative half-precision, (continued)
- [Qemu-devel] [PATCH v5 16/28] target/m68k: Use floatX_silence_nan when we have already checked for SNaN, Richard Henderson, 2018/05/14
- [Qemu-devel] [PATCH v5 15/28] target/hppa: Remove floatX_maybe_silence_nan from conversions, Richard Henderson, 2018/05/14
- [Qemu-devel] [PATCH v5 14/28] fpu/softfloat: re-factor float to float conversions, Richard Henderson, 2018/05/14
- [Qemu-devel] [PATCH v5 17/28] target/mips: Remove floatX_maybe_silence_nan from conversions, Richard Henderson, 2018/05/14
- [Qemu-devel] [PATCH v5 18/28] target/riscv: Remove floatX_maybe_silence_nan from conversions, Richard Henderson, 2018/05/14
- [Qemu-devel] [PATCH v5 19/28] target/s390x: Remove floatX_maybe_silence_nan from conversions, Richard Henderson, 2018/05/14
- [Qemu-devel] [PATCH v5 20/28] fpu/softfloat: Use float*_silence_nan in propagateFloat*NaN, Richard Henderson, 2018/05/14
- Re: [Qemu-devel] [PATCH v5 20/28] fpu/softfloat: Use float*_silence_nan in propagateFloat*NaN,
Alex Bennée <=
- [Qemu-devel] [PATCH v5 23/28] fpu/softfloat: Make is_nan et al available to softfloat-specialize.h, Richard Henderson, 2018/05/14
- [Qemu-devel] [PATCH v5 24/28] fpu/softfloat: Pass FloatClass to pickNaN, Richard Henderson, 2018/05/14
- [Qemu-devel] [PATCH v5 25/28] fpu/softfloat: Pass FloatClass to pickNaNMulAdd, Richard Henderson, 2018/05/14
- [Qemu-devel] [PATCH v5 21/28] fpu/softfloat: Remove floatX_maybe_silence_nan, Richard Henderson, 2018/05/14
- [Qemu-devel] [PATCH v5 22/28] fpu/softfloat: Specialize on snan_bit_is_one, Richard Henderson, 2018/05/14