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[Qemu-devel] [PULL 12/16] target/arm: Implement FCSEL for fp16
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 12/16] target/arm: Implement FCSEL for fp16 |
Date: |
Tue, 15 May 2018 15:07:03 +0100 |
From: Alex Bennée <address@hidden>
These were missed out from the rest of the half-precision work.
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Alex Bennée <address@hidden>
Tested-by: Alex Bennée <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
[rth: Fix erroneous check vs type]
Signed-off-by: Richard Henderson <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-a64.c | 31 +++++++++++++++++++++++++------
1 file changed, 25 insertions(+), 6 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index c078a54fa5..9dacb583ae 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -4903,15 +4903,34 @@ static void disas_fp_csel(DisasContext *s, uint32_t
insn)
unsigned int mos, type, rm, cond, rn, rd;
TCGv_i64 t_true, t_false, t_zero;
DisasCompare64 c;
+ TCGMemOp sz;
mos = extract32(insn, 29, 3);
- type = extract32(insn, 22, 2); /* 0 = single, 1 = double */
+ type = extract32(insn, 22, 2);
rm = extract32(insn, 16, 5);
cond = extract32(insn, 12, 4);
rn = extract32(insn, 5, 5);
rd = extract32(insn, 0, 5);
- if (mos || type > 1) {
+ if (mos) {
+ unallocated_encoding(s);
+ return;
+ }
+
+ switch (type) {
+ case 0:
+ sz = MO_32;
+ break;
+ case 1:
+ sz = MO_64;
+ break;
+ case 3:
+ sz = MO_16;
+ if (arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
+ break;
+ }
+ /* fallthru */
+ default:
unallocated_encoding(s);
return;
}
@@ -4920,11 +4939,11 @@ static void disas_fp_csel(DisasContext *s, uint32_t
insn)
return;
}
- /* Zero extend sreg inputs to 64 bits now. */
+ /* Zero extend sreg & hreg inputs to 64 bits now. */
t_true = tcg_temp_new_i64();
t_false = tcg_temp_new_i64();
- read_vec_element(s, t_true, rn, 0, type ? MO_64 : MO_32);
- read_vec_element(s, t_false, rm, 0, type ? MO_64 : MO_32);
+ read_vec_element(s, t_true, rn, 0, sz);
+ read_vec_element(s, t_false, rm, 0, sz);
a64_test_cc(&c, cond);
t_zero = tcg_const_i64(0);
@@ -4933,7 +4952,7 @@ static void disas_fp_csel(DisasContext *s, uint32_t insn)
tcg_temp_free_i64(t_false);
a64_free_cc(&c);
- /* Note that sregs write back zeros to the high bits,
+ /* Note that sregs & hregs write back zeros to the high bits,
and we've already done the zero-extension. */
write_fp_dreg(s, rd, t_true);
tcg_temp_free_i64(t_true);
--
2.17.0
- [Qemu-devel] [PULL 00/16] target-arm queue, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 04/16] target/arm: Implement FMOV (general) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 07/16] target/arm: Implement FCVT (scalar, fixed-point) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 06/16] target/arm: Implement FCVT (scalar, integer) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 03/16] target/arm: Fix fp_status_f16 tininess before rounding, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 12/16] target/arm: Implement FCSEL for fp16,
Peter Maydell <=
- [Qemu-devel] [PULL 01/16] fpu/softfloat: int_to_float ensure r fully initialised, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 11/16] target/arm: Implement FCMP for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 10/16] target/arm: Implement FP data-processing (3 source) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 08/16] target/arm: Introduce and use read_fp_hreg, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 09/16] target/arm: Implement FP data-processing (2 source) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 02/16] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT), Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 05/16] target/arm: Early exit after unallocated_encoding in disas_fp_int_conv, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 13/16] target/arm: Implement FMOV (immediate) for fp16, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 16/16] tcg: Optionally log FPU state in TCG -d cpu logging, Peter Maydell, 2018/05/15
- [Qemu-devel] [PULL 15/16] sdcard: Correct CRC16 offset in sd_function_switch(), Peter Maydell, 2018/05/15