[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PULL 22/32] target/arm: Implement SVE Integer Arithmetic -
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 22/32] target/arm: Implement SVE Integer Arithmetic - Unpredicated Group |
Date: |
Fri, 18 May 2018 18:19:59 +0100 |
From: Richard Henderson <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/translate-sve.c | 34 ++++++++++++++++++++++++++++++++++
target/arm/sve.decode | 13 +++++++++++++
2 files changed, 47 insertions(+)
diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
index f14bb2196a..d9c4118d46 100644
--- a/target/arm/translate-sve.c
+++ b/target/arm/translate-sve.c
@@ -251,6 +251,40 @@ static bool trans_BIC_zzz(DisasContext *s, arg_rrr_esz *a,
uint32_t insn)
return do_vector3_z(s, tcg_gen_gvec_andc, 0, a->rd, a->rn, a->rm);
}
+/*
+ *** SVE Integer Arithmetic - Unpredicated Group
+ */
+
+static bool trans_ADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ return do_vector3_z(s, tcg_gen_gvec_add, a->esz, a->rd, a->rn, a->rm);
+}
+
+static bool trans_SUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ return do_vector3_z(s, tcg_gen_gvec_sub, a->esz, a->rd, a->rn, a->rm);
+}
+
+static bool trans_SQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ return do_vector3_z(s, tcg_gen_gvec_ssadd, a->esz, a->rd, a->rn, a->rm);
+}
+
+static bool trans_SQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ return do_vector3_z(s, tcg_gen_gvec_sssub, a->esz, a->rd, a->rn, a->rm);
+}
+
+static bool trans_UQADD_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ return do_vector3_z(s, tcg_gen_gvec_usadd, a->esz, a->rd, a->rn, a->rm);
+}
+
+static bool trans_UQSUB_zzz(DisasContext *s, arg_rrr_esz *a, uint32_t insn)
+{
+ return do_vector3_z(s, tcg_gen_gvec_ussub, a->esz, a->rd, a->rn, a->rm);
+}
+
/*
*** SVE Integer Arithmetic - Binary Predicated Group
*/
diff --git a/target/arm/sve.decode b/target/arm/sve.decode
index 5e4335b2ae..58d59c7b77 100644
--- a/target/arm/sve.decode
+++ b/target/arm/sve.decode
@@ -66,6 +66,9 @@
# Three predicate operand, with governing predicate, flag setting
@pd_pg_pn_pm_s ........ . s:1 .. rm:4 .. pg:4 . rn:4 . rd:4 &rprr_s
+# Three operand, vector element size
address@hidden ........ esz:2 . rm:5 ... ... rn:5 rd:5 &rrr_esz
+
# Two register operand, with governing predicate, vector element size
@rdn_pg_rm ........ esz:2 ... ... ... pg:3 rm:5 rd:5 \
&rprr_esz rn=%reg_movprfx
@@ -203,6 +206,16 @@ MLS 00000100 .. 0 ..... 011 ... ..... .....
@rda_pg_rn_rm
MLA 00000100 .. 0 ..... 110 ... ..... ..... @rdn_pg_ra_rm # MAD
MLS 00000100 .. 0 ..... 111 ... ..... ..... @rdn_pg_ra_rm # MSB
+### SVE Integer Arithmetic - Unpredicated Group
+
+# SVE integer add/subtract vectors (unpredicated)
+ADD_zzz 00000100 .. 1 ..... 000 000 ..... ..... @rd_rn_rm
+SUB_zzz 00000100 .. 1 ..... 000 001 ..... ..... @rd_rn_rm
+SQADD_zzz 00000100 .. 1 ..... 000 100 ..... ..... @rd_rn_rm
+UQADD_zzz 00000100 .. 1 ..... 000 101 ..... ..... @rd_rn_rm
+SQSUB_zzz 00000100 .. 1 ..... 000 110 ..... ..... @rd_rn_rm
+UQSUB_zzz 00000100 .. 1 ..... 000 111 ..... ..... @rd_rn_rm
+
### SVE Logical - Unpredicated Group
# SVE bitwise logical operations (unpredicated)
--
2.17.0
- [Qemu-devel] [PULL 18/32] target/arm: Implement SVE bitwise shift by vector (predicated), (continued)
- [Qemu-devel] [PULL 18/32] target/arm: Implement SVE bitwise shift by vector (predicated), Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 24/32] target/arm: Implement SVE Stack Allocation Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 20/32] target/arm: Implement SVE Integer Arithmetic - Unary Predicated Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 14/32] target/arm: Implement SVE Predicate Misc Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 16/32] target/arm: Implement SVE Integer Reduction Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 15/32] target/arm: Implement SVE Integer Binary Arithmetic - Predicated Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 23/32] target/arm: Implement SVE Index Generation Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 17/32] target/arm: Implement SVE bitwise shift by immediate (predicated), Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 21/32] target/arm: Implement SVE Integer Multiply-Add Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 30/32] target/arm: Implement SVE Bitwise Immediate Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 22/32] target/arm: Implement SVE Integer Arithmetic - Unpredicated Group,
Peter Maydell <=
- [Qemu-devel] [PULL 29/32] target/arm: Implement SVE Element Count Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 31/32] target/arm: Implement SVE Integer Wide Immediate - Predicated Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 25/32] target/arm: Implement SVE Bitwise Shift - Unpredicated Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 27/32] target/arm: Implement SVE floating-point exponential accelerator, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 28/32] target/arm: Implement SVE floating-point trig select coefficient, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 32/32] target/arm: Implement SVE Permute - Extract Group, Peter Maydell, 2018/05/18
- [Qemu-devel] [PULL 26/32] target/arm: Implement SVE Compute Vector Address Group, Peter Maydell, 2018/05/18
- Re: [Qemu-devel] [PULL 00/32] target-arm queue, Peter Maydell, 2018/05/18