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Re: [Qemu-devel] [qemu PATCH v2 3/4] nvdimm, acpi: support NFIT platform


From: Ross Zwisler
Subject: Re: [Qemu-devel] [qemu PATCH v2 3/4] nvdimm, acpi: support NFIT platform capabilities
Date: Mon, 21 May 2018 09:54:49 -0600
User-agent: Mutt/1.9.2 (2017-12-15)

On Fri, May 18, 2018 at 04:37:10PM +0000, Elliott, Robert (Persistent Memory) 
wrote:
> 
> 
> ...
> > Would it help to show them in hex?
> > 
> >   As of ACPI 6.2 Errata A, the following values are valid for the bottom
> >   two bits:
> > 
> >   0x2 - Memory Controller Flush to NVDIMM Durability on Power Loss Capable.
> >   0x3 - CPU Cache Flush to NVDIMM Durability on Power Loss Capable.
> 
> Yes, that helps (unless the parser for that command-line does not 
> accept hex values).

Yep, the command-line parser does accept hex values.  I ended up just trying
to make the text clearer, though.

> It would also help to make the text be:
>       "CPU Cache and Memory Controller Flush"

My descriptions for the bits are coming straight out of ACPI. :)  I'd prefer
to stay consistent with what's written in the spec.



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