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Re: [Qemu-devel] [PATCH v1 20/30] RISC-V: Add misa to DisasContext
From: |
Philippe Mathieu-Daudé |
Subject: |
Re: [Qemu-devel] [PATCH v1 20/30] RISC-V: Add misa to DisasContext |
Date: |
Wed, 23 May 2018 09:42:38 -0300 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.7.0 |
On 05/22/2018 09:15 PM, Michael Clark wrote:
> gen methods should access state from DisasContext. Add misa
> field to the DisasContext struct and remove CPURISCVState
> argument from all gen methods.
>
> Cc: Palmer Dabbelt <address@hidden>
> Cc: Sagar Karandikar <address@hidden>
> Cc: Bastian Koppelmann <address@hidden>
> Cc: Alistair Francis <address@hidden>
> Cc: Emilio G. Cota <address@hidden>
> Signed-off-by: Michael Clark <address@hidden>
> Reviewed-by: Richard Henderson <address@hidden>
I already reviewed this one:
http://lists.nongnu.org/archive/html/qemu-devel/2018-05/msg02255.html
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
> ---
> target/riscv/translate.c | 78
> ++++++++++++++++++++++++++----------------------
> 1 file changed, 42 insertions(+), 36 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index a980611eb611..fd21b133a5a4 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -45,6 +45,7 @@ typedef struct DisasContext {
> target_ulong pc_succ_insn;
> uint32_t opcode;
> uint32_t mstatus_fs;
> + uint32_t misa;
> uint32_t mem_idx;
> /* Remember the rounding mode encoded in the previous fp instruction,
> which we have already installed into env->fp_status. Or -1 for
> @@ -74,6 +75,11 @@ static const int tcg_memop_lookup[8] = {
> #define CASE_OP_32_64(X) case X
> #endif
>
> +static inline bool has_ext(DisasContext *ctx, uint32_t ext)
> +{
> + return ctx->misa & ext;
> +}
> +
> static void generate_exception(DisasContext *ctx, int excp)
> {
> tcg_gen_movi_tl(cpu_pc, ctx->base.pc_next);
> @@ -505,14 +511,13 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t
> opc, int rd,
> tcg_temp_free(source1);
> }
>
> -static void gen_jal(CPURISCVState *env, DisasContext *ctx, int rd,
> - target_ulong imm)
> +static void gen_jal(DisasContext *ctx, int rd, target_ulong imm)
> {
> target_ulong next_pc;
>
> /* check misaligned: */
> next_pc = ctx->base.pc_next + imm;
> - if (!riscv_has_ext(env, RVC)) {
> + if (!has_ext(ctx, RVC)) {
> if ((next_pc & 0x3) != 0) {
> gen_exception_inst_addr_mis(ctx);
> return;
> @@ -526,8 +531,8 @@ static void gen_jal(CPURISCVState *env, DisasContext
> *ctx, int rd,
> ctx->base.is_jmp = DISAS_NORETURN;
> }
>
> -static void gen_jalr(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
> - int rd, int rs1, target_long imm)
> +static void gen_jalr(DisasContext *ctx, uint32_t opc, int rd, int rs1,
> + target_long imm)
> {
> /* no chaining with JALR */
> TCGLabel *misaligned = NULL;
> @@ -539,7 +544,7 @@ static void gen_jalr(CPURISCVState *env, DisasContext
> *ctx, uint32_t opc,
> tcg_gen_addi_tl(cpu_pc, cpu_pc, imm);
> tcg_gen_andi_tl(cpu_pc, cpu_pc, (target_ulong)-2);
>
> - if (!riscv_has_ext(env, RVC)) {
> + if (!has_ext(ctx, RVC)) {
> misaligned = gen_new_label();
> tcg_gen_andi_tl(t0, cpu_pc, 0x2);
> tcg_gen_brcondi_tl(TCG_COND_NE, t0, 0x0, misaligned);
> @@ -564,8 +569,8 @@ static void gen_jalr(CPURISCVState *env, DisasContext
> *ctx, uint32_t opc,
> tcg_temp_free(t0);
> }
>
> -static void gen_branch(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
> - int rs1, int rs2, target_long bimm)
> +static void gen_branch(DisasContext *ctx, uint32_t opc, int rs1, int rs2,
> + target_long bimm)
> {
> TCGLabel *l = gen_new_label();
> TCGv source1, source2;
> @@ -602,7 +607,7 @@ static void gen_branch(CPURISCVState *env, DisasContext
> *ctx, uint32_t opc,
>
> gen_goto_tb(ctx, 1, ctx->pc_succ_insn);
> gen_set_label(l); /* branch taken */
> - if (!riscv_has_ext(env, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
> + if (!has_ext(ctx, RVC) && ((ctx->base.pc_next + bimm) & 0x3)) {
> /* misaligned */
> gen_exception_inst_addr_mis(ctx);
> } else {
> @@ -1311,8 +1316,8 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t
> opc, int rd,
> }
> }
>
> -static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc,
> - int rd, int rs1, int csr)
> +static void gen_system(DisasContext *ctx, uint32_t opc, int rd, int rs1,
> + int csr)
> {
> TCGv source1, csr_store, dest, rs1_pass, imm_rs1;
> source1 = tcg_temp_new();
> @@ -1354,7 +1359,7 @@ static void gen_system(CPURISCVState *env, DisasContext
> *ctx, uint32_t opc,
> gen_exception_illegal(ctx);
> break;
> case 0x102: /* SRET */
> - if (riscv_has_ext(env, RVS)) {
> + if (has_ext(ctx, RVS)) {
> gen_helper_sret(cpu_pc, cpu_env, cpu_pc);
> tcg_gen_exit_tb(0); /* no chaining */
> ctx->base.is_jmp = DISAS_NORETURN;
> @@ -1495,7 +1500,7 @@ static void decode_RV32_64C0(DisasContext *ctx)
> }
> }
>
> -static void decode_RV32_64C1(CPURISCVState *env, DisasContext *ctx)
> +static void decode_RV32_64C1(DisasContext *ctx)
> {
> uint8_t funct3 = extract32(ctx->opcode, 13, 3);
> uint8_t rd_rs1 = GET_C_RS1(ctx->opcode);
> @@ -1515,7 +1520,7 @@ static void decode_RV32_64C1(CPURISCVState *env,
> DisasContext *ctx)
> GET_C_IMM(ctx->opcode));
> #else
> /* C.JAL(RV32) -> jal x1, offset[11:1] */
> - gen_jal(env, ctx, 1, GET_C_J_IMM(ctx->opcode));
> + gen_jal(ctx, 1, GET_C_J_IMM(ctx->opcode));
> #endif
> break;
> case 2:
> @@ -1594,22 +1599,22 @@ static void decode_RV32_64C1(CPURISCVState *env,
> DisasContext *ctx)
> break;
> case 5:
> /* C.J -> jal x0, offset[11:1]*/
> - gen_jal(env, ctx, 0, GET_C_J_IMM(ctx->opcode));
> + gen_jal(ctx, 0, GET_C_J_IMM(ctx->opcode));
> break;
> case 6:
> /* C.BEQZ -> beq rs1', x0, offset[8:1]*/
> rs1s = GET_C_RS1S(ctx->opcode);
> - gen_branch(env, ctx, OPC_RISC_BEQ, rs1s, 0,
> GET_C_B_IMM(ctx->opcode));
> + gen_branch(ctx, OPC_RISC_BEQ, rs1s, 0, GET_C_B_IMM(ctx->opcode));
> break;
> case 7:
> /* C.BNEZ -> bne rs1', x0, offset[8:1]*/
> rs1s = GET_C_RS1S(ctx->opcode);
> - gen_branch(env, ctx, OPC_RISC_BNE, rs1s, 0,
> GET_C_B_IMM(ctx->opcode));
> + gen_branch(ctx, OPC_RISC_BNE, rs1s, 0, GET_C_B_IMM(ctx->opcode));
> break;
> }
> }
>
> -static void decode_RV32_64C2(CPURISCVState *env, DisasContext *ctx)
> +static void decode_RV32_64C2(DisasContext *ctx)
> {
> uint8_t rd, rs2;
> uint8_t funct3 = extract32(ctx->opcode, 13, 3);
> @@ -1643,7 +1648,7 @@ static void decode_RV32_64C2(CPURISCVState *env,
> DisasContext *ctx)
> if (extract32(ctx->opcode, 12, 1) == 0) {
> if (rs2 == 0) {
> /* C.JR -> jalr x0, rs1, 0*/
> - gen_jalr(env, ctx, OPC_RISC_JALR, 0, rd, 0);
> + gen_jalr(ctx, OPC_RISC_JALR, 0, rd, 0);
> } else {
> /* C.MV -> add rd, x0, rs2 */
> gen_arith(ctx, OPC_RISC_ADD, rd, 0, rs2);
> @@ -1651,11 +1656,11 @@ static void decode_RV32_64C2(CPURISCVState *env,
> DisasContext *ctx)
> } else {
> if (rd == 0) {
> /* C.EBREAK -> ebreak*/
> - gen_system(env, ctx, OPC_RISC_ECALL, 0, 0, 0x1);
> + gen_system(ctx, OPC_RISC_ECALL, 0, 0, 0x1);
> } else {
> if (rs2 == 0) {
> /* C.JALR -> jalr x1, rs1, 0*/
> - gen_jalr(env, ctx, OPC_RISC_JALR, 1, rd, 0);
> + gen_jalr(ctx, OPC_RISC_JALR, 1, rd, 0);
> } else {
> /* C.ADD -> add rd, rd, rs2 */
> gen_arith(ctx, OPC_RISC_ADD, rd, rd, rs2);
> @@ -1687,7 +1692,7 @@ static void decode_RV32_64C2(CPURISCVState *env,
> DisasContext *ctx)
> }
> }
>
> -static void decode_RV32_64C(CPURISCVState *env, DisasContext *ctx)
> +static void decode_RV32_64C(DisasContext *ctx)
> {
> uint8_t op = extract32(ctx->opcode, 0, 2);
>
> @@ -1696,15 +1701,15 @@ static void decode_RV32_64C(CPURISCVState *env,
> DisasContext *ctx)
> decode_RV32_64C0(ctx);
> break;
> case 1:
> - decode_RV32_64C1(env, ctx);
> + decode_RV32_64C1(ctx);
> break;
> case 2:
> - decode_RV32_64C2(env, ctx);
> + decode_RV32_64C2(ctx);
> break;
> }
> }
>
> -static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx)
> +static void decode_RV32_64G(DisasContext *ctx)
> {
> int rs1;
> int rs2;
> @@ -1739,13 +1744,13 @@ static void decode_RV32_64G(CPURISCVState *env,
> DisasContext *ctx)
> break;
> case OPC_RISC_JAL:
> imm = GET_JAL_IMM(ctx->opcode);
> - gen_jal(env, ctx, rd, imm);
> + gen_jal(ctx, rd, imm);
> break;
> case OPC_RISC_JALR:
> - gen_jalr(env, ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm);
> + gen_jalr(ctx, MASK_OP_JALR(ctx->opcode), rd, rs1, imm);
> break;
> case OPC_RISC_BRANCH:
> - gen_branch(env, ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2,
> + gen_branch(ctx, MASK_OP_BRANCH(ctx->opcode), rs1, rs2,
> GET_B_IMM(ctx->opcode));
> break;
> case OPC_RISC_LOAD:
> @@ -1818,7 +1823,7 @@ static void decode_RV32_64G(CPURISCVState *env,
> DisasContext *ctx)
> #endif
> break;
> case OPC_RISC_SYSTEM:
> - gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
> + gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
> (ctx->opcode & 0xFFF00000) >> 20);
> break;
> default:
> @@ -1827,29 +1832,31 @@ static void decode_RV32_64G(CPURISCVState *env,
> DisasContext *ctx)
> }
> }
>
> -static void decode_opc(CPURISCVState *env, DisasContext *ctx)
> +static void decode_opc(DisasContext *ctx)
> {
> /* check for compressed insn */
> if (extract32(ctx->opcode, 0, 2) != 3) {
> - if (!riscv_has_ext(env, RVC)) {
> + if (!has_ext(ctx, RVC)) {
> gen_exception_illegal(ctx);
> } else {
> ctx->pc_succ_insn = ctx->base.pc_next + 2;
> - decode_RV32_64C(env, ctx);
> + decode_RV32_64C(ctx);
> }
> } else {
> ctx->pc_succ_insn = ctx->base.pc_next + 4;
> - decode_RV32_64G(env, ctx);
> + decode_RV32_64G(ctx);
> }
> }
>
> -static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState
> *cs)
> +static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState
> *cpu)
> {
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> + CPURISCVState *env = cpu->env_ptr;
>
> ctx->pc_succ_insn = ctx->base.pc_first;
> ctx->mem_idx = ctx->base.tb->flags & TB_FLAGS_MMU_MASK;
> ctx->mstatus_fs = ctx->base.tb->flags & TB_FLAGS_MSTATUS_FS;
> + ctx->misa = env->misa;
> ctx->frm = -1; /* unknown rounding mode */
> }
>
> @@ -1880,14 +1887,13 @@ static bool
> riscv_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cpu,
> return true;
> }
>
> -
> static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
> {
> DisasContext *ctx = container_of(dcbase, DisasContext, base);
> CPURISCVState *env = cpu->env_ptr;
>
> ctx->opcode = cpu_ldl_code(env, ctx->base.pc_next);
> - decode_opc(env, ctx);
> + decode_opc(ctx);
> ctx->base.pc_next = ctx->pc_succ_insn;
>
> if (ctx->base.is_jmp == DISAS_NEXT) {
>
- Re: [Qemu-devel] [PATCH v1 15/30] RISC-V: Add hartid and \n to interrupt logging, (continued)
- [Qemu-devel] [PATCH v1 16/30] RISC-V: Use riscv prefix consistently on cpu helpers, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 17/30] RISC-V: Replace __builtin_popcount with ctpop8 in PLIC, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 18/30] RISC-V: Add missing free for plic_hart_config, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 19/30] RISC-V: Allow interrupt controllers to claim interrupts, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 20/30] RISC-V: Add misa to DisasContext, Michael Clark, 2018/05/22
- Re: [Qemu-devel] [PATCH v1 20/30] RISC-V: Add misa to DisasContext,
Philippe Mathieu-Daudé <=
- [Qemu-devel] [PATCH v1 21/30] RISC-V: Add misa.MAFD checks to translate, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 22/30] RISC-V: Add misa runtime write support, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 23/30] RISC-V: Fix CLINT timecmp low 32-bit writes, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 24/30] RISC-V: Fix PLIC pending bitfield reads, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 25/30] RISC-V: Enable second UART on sifive_e and sifive_u, Michael Clark, 2018/05/22
- [Qemu-devel] [PATCH v1 26/30] RISC-V: Remove unnecessary disassembler constraints, Michael Clark, 2018/05/22