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[Qemu-devel] [PULL 03/25] hw/intc/arm_gicv3: Fix APxR<n> register dispat
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 03/25] hw/intc/arm_gicv3: Fix APxR<n> register dispatching |
Date: |
Thu, 31 May 2018 15:23:35 +0100 |
From: Jan Kiszka <address@hidden>
There was a nasty flip in identifying which register group an access is
targeting. The issue caused spuriously raised priorities of the guest
when handing CPUs over in the Jailhouse hypervisor.
Cc: address@hidden
Signed-off-by: Jan Kiszka <address@hidden>
Message-id: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Peter Maydell <address@hidden>
---
hw/intc/arm_gicv3_cpuif.c | 12 ++++++------
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index cb9a3a542d..5c89be1af0 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -427,7 +427,7 @@ static uint64_t icv_ap_read(CPUARMState *env, const
ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
uint64_t value = cs->ich_apr[grp][regno];
trace_gicv3_icv_ap_read(ri->crm & 1, regno, gicv3_redist_affid(cs), value);
@@ -439,7 +439,7 @@ static void icv_ap_write(CPUARMState *env, const
ARMCPRegInfo *ri,
{
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
trace_gicv3_icv_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs),
value);
@@ -1461,7 +1461,7 @@ static uint64_t icc_ap_read(CPUARMState *env, const
ARMCPRegInfo *ri)
uint64_t value;
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
+ int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
return icv_ap_read(env, ri);
@@ -1483,7 +1483,7 @@ static void icc_ap_write(CPUARMState *env, const
ARMCPRegInfo *ri,
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1;
+ int grp = (ri->crm & 1) ? GICV3_G1 : GICV3_G0;
if (icv_access(env, grp == GICV3_G0 ? HCR_FMO : HCR_IMO)) {
icv_ap_write(env, ri, value);
@@ -2292,7 +2292,7 @@ static uint64_t ich_ap_read(CPUARMState *env, const
ARMCPRegInfo *ri)
{
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
uint64_t value;
value = cs->ich_apr[grp][regno];
@@ -2305,7 +2305,7 @@ static void ich_ap_write(CPUARMState *env, const
ARMCPRegInfo *ri,
{
GICv3CPUState *cs = icc_cs_from_env(env);
int regno = ri->opc2 & 3;
- int grp = ri->crm & 1 ? GICV3_G0 : GICV3_G1NS;
+ int grp = (ri->crm & 1) ? GICV3_G1NS : GICV3_G0;
trace_gicv3_ich_ap_write(ri->crm & 1, regno, gicv3_redist_affid(cs),
value);
--
2.17.1
- [Qemu-devel] [PULL 00/25] target-arm queue, Peter Maydell, 2018/05/31
- [Qemu-devel] [PULL 11/25] Make tb_invalidate_phys_addr() take a MemTxAttrs argument, Peter Maydell, 2018/05/31
- [Qemu-devel] [PULL 09/25] Correct CPACR reset value for v7 cores, Peter Maydell, 2018/05/31
- [Qemu-devel] [PULL 12/25] Make address_space_translate{, _cached}() take a MemTxAttrs argument, Peter Maydell, 2018/05/31
- [Qemu-devel] [PULL 10/25] memory.h: Improve IOMMU related documentation, Peter Maydell, 2018/05/31
- [Qemu-devel] [PULL 08/25] xlnx-zdma: Correct mem leaks and memset to zero on desc unaligned errors, Peter Maydell, 2018/05/31
- [Qemu-devel] [PULL 03/25] hw/intc/arm_gicv3: Fix APxR<n> register dispatching,
Peter Maydell <=
- [Qemu-devel] [PULL 16/25] Make memory_region_access_valid() take a MemTxAttrs argument, Peter Maydell, 2018/05/31
- [Qemu-devel] [PULL 13/25] Make address_space_map() take a MemTxAttrs argument, Peter Maydell, 2018/05/31
- [Qemu-devel] [PULL 15/25] Make flatview_extend_translation() take a MemTxAttrs argument, Peter Maydell, 2018/05/31
- [Qemu-devel] [PULL 07/25] arm: fix malloc type mismatch, Peter Maydell, 2018/05/31
- [Qemu-devel] [PULL 06/25] arm: fix qemu crash on startup with -bios option, Peter Maydell, 2018/05/31
- [Qemu-devel] [PULL 04/25] arm_gicv3_kvm: increase clroffset accordingly, Peter Maydell, 2018/05/31
- [Qemu-devel] [PULL 02/25] MAINTAINERS: Add entries for newer MPS2 boards and devices, Peter Maydell, 2018/05/31
- [Qemu-devel] [PULL 18/25] Make flatview_access_valid() take a MemTxAttrs argument, Peter Maydell, 2018/05/31
- [Qemu-devel] [PULL 20/25] Make address_space_get_iotlb_entry() take a MemTxAttrs argument, Peter Maydell, 2018/05/31
- [Qemu-devel] [PULL 21/25] Make flatview_do_translate() take a MemTxAttrs argument, Peter Maydell, 2018/05/31