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Re: [Qemu-devel] [PATCH] m25p80: add support for two bytes WRSR for Macr
From: |
Alistair Francis |
Subject: |
Re: [Qemu-devel] [PATCH] m25p80: add support for two bytes WRSR for Macronix chips |
Date: |
Mon, 11 Jun 2018 15:03:47 -0700 |
On Mon, Jun 11, 2018 at 10:18 AM, Cédric Le Goater <address@hidden> wrote:
> On 06/11/2018 07:15 PM, Cédric Le Goater wrote:
>> On Macronix chips, two bytes can written to the WRSR. First byte will
>> configure the status register and the second the configuration
>> register. It is important to save the configuration value as it
>> contains the dummy cycle setting when using dual or quad IO mode.
>>
>> Signed-off-by: Cédric Le Goater <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Alistair
>> ---
>> hw/block/m25p80.c | 1 +
>> 1 file changed, 1 insertion(+)
>>
>> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
>> index b49c8e9caa04..29775e055a24 100644
>> --- a/hw/block/m25p80.c
>> +++ b/hw/block/m25p80.c
>> @@ -699,6 +699,7 @@ static void complete_collecting_data(Flash *s)
>> case MAN_MACRONIX:
>> s->quad_enable = extract32(s->data[0], 6, 1);
>> if (s->len > 1) {
>> + s->volatile_cfg = s->data[1];
>> s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
>> }
>> break;
>>
>
> I sent this patch to qemu-ppc instead of qemu-devel ...
>
> Sorry for the noise.
>
> C.
>