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[Qemu-devel] [PATCH v4b 01/18] target/arm: Extend vec_reg_offset to larg
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v4b 01/18] target/arm: Extend vec_reg_offset to larger sizes |
Date: |
Tue, 12 Jun 2018 15:56:24 -1000 |
Rearrange the arithmetic so that we are agnostic about the total size
of the vector and the size of the element. This will allow us to index
up to the 32nd byte and with 16-byte elements.
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/translate-a64.h | 26 +++++++++++++++++---------
1 file changed, 17 insertions(+), 9 deletions(-)
diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h
index dd9c09f89b..63d958cf50 100644
--- a/target/arm/translate-a64.h
+++ b/target/arm/translate-a64.h
@@ -67,18 +67,26 @@ static inline void assert_fp_access_checked(DisasContext *s)
static inline int vec_reg_offset(DisasContext *s, int regno,
int element, TCGMemOp size)
{
- int offs = 0;
+ int element_size = 1 << size;
+ int offs = element * element_size;
#ifdef HOST_WORDS_BIGENDIAN
/* This is complicated slightly because vfp.zregs[n].d[0] is
- * still the low half and vfp.zregs[n].d[1] the high half
- * of the 128 bit vector, even on big endian systems.
- * Calculate the offset assuming a fully bigendian 128 bits,
- * then XOR to account for the order of the two 64 bit halves.
+ * still the lowest and vfp.zregs[n].d[15] the highest of the
+ * 256 byte vector, even on big endian systems.
+ *
+ * Calculate the offset assuming fully little-endian,
+ * then XOR to account for the order of the 8-byte units.
+ *
+ * For 16 byte elements, the two 8 byte halves will not form a
+ * host int128 if the host is bigendian, since they're in the
+ * wrong order. However the only 16 byte operation we have is
+ * a move, so we can ignore this for the moment. More complicated
+ * operations will have to special case loading and storing from
+ * the zregs array.
*/
- offs += (16 - ((element + 1) * (1 << size)));
- offs ^= 8;
-#else
- offs += element * (1 << size);
+ if (element_size < 8) {
+ offs ^= 8 - element_size;
+ }
#endif
offs += offsetof(CPUARMState, vfp.zregs[regno]);
assert_fp_access_checked(s);
--
2.17.1
- [Qemu-devel] [PATCH v4b 00/18] target/arm: SVE instructions, part 2, Richard Henderson, 2018/06/12
- [Qemu-devel] [PATCH v4b 01/18] target/arm: Extend vec_reg_offset to larger sizes,
Richard Henderson <=
- [Qemu-devel] [PATCH v4b 02/18] target/arm: Implement SVE Permute - Unpredicated Group, Richard Henderson, 2018/06/12
- [Qemu-devel] [PATCH v4b 03/18] target/arm: Implement SVE Permute - Predicates Group, Richard Henderson, 2018/06/12
- [Qemu-devel] [PATCH v4b 04/18] target/arm: Implement SVE Permute - Interleaving Group, Richard Henderson, 2018/06/12
- [Qemu-devel] [PATCH v4b 05/18] target/arm: Implement SVE compress active elements, Richard Henderson, 2018/06/12
- [Qemu-devel] [PATCH v4b 07/18] target/arm: Implement SVE copy to vector (predicated), Richard Henderson, 2018/06/12
- [Qemu-devel] [PATCH v4b 06/18] target/arm: Implement SVE conditionally broadcast/extract element, Richard Henderson, 2018/06/12
- [Qemu-devel] [PATCH v4b 08/18] target/arm: Implement SVE reverse within elements, Richard Henderson, 2018/06/12
- [Qemu-devel] [PATCH v4b 09/18] target/arm: Implement SVE vector splice (predicated), Richard Henderson, 2018/06/12
- [Qemu-devel] [PATCH v4b 10/18] target/arm: Implement SVE Select Vectors Group, Richard Henderson, 2018/06/12
- [Qemu-devel] [PATCH v4b 11/18] target/arm: Implement SVE Integer Compare - Vectors Group, Richard Henderson, 2018/06/12