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[Qemu-devel] [PATCH 107/113] i386: Define the Virt SSBD MSR and handling
From: |
Michael Roth |
Subject: |
[Qemu-devel] [PATCH 107/113] i386: Define the Virt SSBD MSR and handling of it (CVE-2018-3639) |
Date: |
Mon, 18 Jun 2018 20:43:13 -0500 |
From: Konrad Rzeszutek Wilk <address@hidden>
"Some AMD processors only support a non-architectural means of enabling
speculative store bypass disable (SSBD). To allow a simplified view of
this to a guest, an architectural definition has been created through a new
CPUID bit, 0x80000008_EBX[25], and a new MSR, 0xc001011f. With this, a
hypervisor can virtualize the existence of this definition and provide an
architectural method for using SSBD to a guest.
Add the new CPUID feature, the new MSR and update the existing SSBD
support to use this MSR when present." (from x86/speculation: Add virtualized
speculative store bypass disable support in Linux).
Signed-off-by: Konrad Rzeszutek Wilk <address@hidden>
Reviewed-by: Daniel P. Berrangé <address@hidden>
Signed-off-by: Daniel P. Berrangé <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Eduardo Habkost <address@hidden>
(cherry picked from commit cfeea0c021db6234c154dbc723730e81553924ff)
Conflicts:
target/i386/kvm.c
target/i386/machine.c
* drop context dep on b77146e9a
Signed-off-by: Michael Roth <address@hidden>
---
target/i386/cpu.h | 2 ++
target/i386/kvm.c | 16 ++++++++++++++--
target/i386/machine.c | 20 ++++++++++++++++++++
3 files changed, 36 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 422d99d80c..3cc1136535 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -336,6 +336,7 @@
#define MSR_IA32_FEATURE_CONTROL 0x0000003a
#define MSR_TSC_ADJUST 0x0000003b
#define MSR_IA32_SPEC_CTRL 0x48
+#define MSR_VIRT_SSBD 0xc001011f
#define MSR_IA32_TSCDEADLINE 0x6e0
#define FEATURE_CONTROL_LOCKED (1<<0)
@@ -1089,6 +1090,7 @@ typedef struct CPUX86State {
uint32_t pkru;
uint64_t spec_ctrl;
+ uint64_t virt_ssbd;
/* End of state preserved by INIT (dummy marker). */
struct {} end_init_save;
diff --git a/target/i386/kvm.c b/target/i386/kvm.c
index 3ac5302bc5..15001beeda 100644
--- a/target/i386/kvm.c
+++ b/target/i386/kvm.c
@@ -92,6 +92,7 @@ static bool has_msr_hv_stimer;
static bool has_msr_hv_frequencies;
static bool has_msr_xss;
static bool has_msr_spec_ctrl;
+static bool has_msr_virt_ssbd;
static bool has_msr_architectural_pmu;
static uint32_t num_architectural_pmu_counters;
@@ -1148,6 +1149,9 @@ static int kvm_get_supported_msrs(KVMState *s)
case MSR_IA32_SPEC_CTRL:
has_msr_spec_ctrl = true;
break;
+ case MSR_VIRT_SSBD:
+ has_msr_virt_ssbd = true;
+ break;
}
}
}
@@ -1633,6 +1637,10 @@ static int kvm_put_msrs(X86CPU *cpu, int level)
if (has_msr_spec_ctrl) {
kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, env->spec_ctrl);
}
+ if (has_msr_virt_ssbd) {
+ kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd);
+ }
+
#ifdef TARGET_X86_64
if (lm_capable_kernel) {
kvm_msr_entry_add(cpu, MSR_CSTAR, env->cstar);
@@ -2009,8 +2017,9 @@ static int kvm_get_msrs(X86CPU *cpu)
if (has_msr_spec_ctrl) {
kvm_msr_entry_add(cpu, MSR_IA32_SPEC_CTRL, 0);
}
-
-
+ if (has_msr_virt_ssbd) {
+ kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0);
+ }
if (!env->tsc_valid) {
kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0);
env->tsc_valid = !runstate_is_running();
@@ -2361,6 +2370,9 @@ static int kvm_get_msrs(X86CPU *cpu)
case MSR_IA32_SPEC_CTRL:
env->spec_ctrl = msrs[i].data;
break;
+ case MSR_VIRT_SSBD:
+ env->virt_ssbd = msrs[i].data;
+ break;
}
}
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 361c05aedf..1c070fb644 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -837,6 +837,25 @@ static const VMStateDescription vmstate_spec_ctrl = {
}
};
+static bool virt_ssbd_needed(void *opaque)
+{
+ X86CPU *cpu = opaque;
+ CPUX86State *env = &cpu->env;
+
+ return env->virt_ssbd != 0;
+}
+
+static const VMStateDescription vmstate_msr_virt_ssbd = {
+ .name = "cpu/virt_ssbd",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = virt_ssbd_needed,
+ .fields = (VMStateField[]){
+ VMSTATE_UINT64(env.virt_ssbd, X86CPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
VMStateDescription vmstate_x86_cpu = {
.name = "cpu",
.version_id = 12,
@@ -957,6 +976,7 @@ VMStateDescription vmstate_x86_cpu = {
#endif
&vmstate_spec_ctrl,
&vmstate_mcg_ext_ctl,
+ &vmstate_msr_virt_ssbd,
NULL
}
};
--
2.11.0
- [Qemu-devel] [PATCH 00/113] Patch Round-up for stable 2.11.2, freeze on 2018-06-22, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 099/113] ahci: fix PxCI register race, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 100/113] arm_gicv3_kvm: kvm_dist_get/put: skip the registers banked by GICR, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 009/113] spapr: use spapr->vsmt to compute VCPU ids, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 101/113] block: Make bdrv_is_writable() public, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 102/113] qcow2: Do not mark inactive images corrupt, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 103/113] iotests: Add case for a corrupted inactive image, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 104/113] throttle: Fix crash on reopen, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 105/113] vga: fix region calculation, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 106/113] i386: define the 'ssbd' CPUID feature bit (CVE-2018-3639), Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 107/113] i386: Define the Virt SSBD MSR and handling of it (CVE-2018-3639),
Michael Roth <=
- [Qemu-devel] [PATCH 108/113] i386: define the AMD 'virt-ssbd' CPUID feature bit (CVE-2018-3639), Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 109/113] tap: set vhostfd passed from qemu cli to non-blocking, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 110/113] vhost-user: delete net client if necessary, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 010/113] spapr: move VCPU calculation to core machine code, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 111/113] qemu-img: Fix assert when mapping unaligned raw file, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 112/113] iotests: Add test 221 to catch qemu-img map regression, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 113/113] arm_gicv3_kvm: kvm_dist_get/put_priority: skip the registers banked by GICR_IPRIORITYR, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 011/113] target/ppc: Clarify compat mode max_threads value, Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 012/113] spapr: rename spapr_vcpu_id() to spapr_get_vcpu_id(), Michael Roth, 2018/06/18
- [Qemu-devel] [PATCH 013/113] spapr: consolidate the VCPU id numbering logic in a single place, Michael Roth, 2018/06/18