Re: [Qemu-devel] [PATCH 14/35] target/mips: Add nanoMIPS p_lsx instructions

[Richard Henderson]

On 06/20/2018 05:05 AM, Yongbok Kim wrote:
> Add nanoMIPS p_lsx and LSA instructions
> 
> Signed-off-by: Yongbok Kim <address@hidden>
> ---
>  target/mips/translate.c | 139 
> +++++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 138 insertions(+), 1 deletion(-)
> 
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index a581330..819cfd9 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -16579,6 +16579,132 @@ static void 
> gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx)
>      }
>  }
>  
> +
> +static void gen_p_lsx(DisasContext *ctx, int rd, int rs, int rt)
> +{
> +    TCGv t0, t1;
> +    t0 = tcg_temp_new();
> +    t1 = tcg_temp_new();
> +    tcg_gen_movi_tl(t1, 0);
> +    if (rs == 0) {
> +        tcg_gen_movi_tl(t0, 0);
> +    } else {
> +        gen_load_gpr(t0, rs);
> +    }

gen_load_gpr already does exactly this == 0 test.

> +    if (((ctx->opcode >> 6) & 1) == 1) {
> +        /* PP.LSXS instructions require shifting */
> +        switch ((ctx->opcode >> 7) & 0xf) {
> +        case NM_LHXS:
> +        case NM_SHXS:
> +        case NM_LHUXS:
> +            tcg_gen_shli_tl(t0, t0, 1);
> +            break;
> +        case NM_LWXS:
> +        case NM_SWXS:
> +        case NM_LWC1XS:
> +        case NM_SWC1XS:
> +            tcg_gen_shli_tl(t0, t0, 2);
> +            break;
> +        case NM_LDC1XS:
> +        case NM_SDC1XS:
> +            tcg_gen_shli_tl(t0, t0, 3);
> +            break;
> +        }
> +    }

If you would set a TCGMemOp mop variable in the first switch, then the shift is

  tcg_gen_shli_tl(t0, t0, mop * MO_SIZE);

> +    switch ((ctx->opcode >> 7) & 0xf) {
> +    case NM_LBX:
> +        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
> +                           MO_SB);
> +        gen_store_gpr(t0, rd);
> +        break;
> +    case NM_LHX:
> +    /*case NM_LHXS:*/
> +        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
> +                           MO_TESW);
> +        gen_store_gpr(t0, rd);
> +        break;
> +    case NM_LWX:
> +    /*case NM_LWXS:*/
> +        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
> +                           MO_TESL);
> +        gen_store_gpr(t0, rd);
> +        break;
> +    case NM_LBUX:
> +        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
> +                           MO_UB);
> +        gen_store_gpr(t0, rd);
> +        break;
> +    case NM_LHUX:
> +    /*case NM_LHUXS:*/
> +        tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx,
> +                           MO_TEUW);
> +        gen_store_gpr(t0, rd);
> +        break;

And all of these cases unify to

  tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, mop);

> +    case NM_SBX:
> +        gen_load_gpr(t1, rd);
> +        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
> +                           MO_8);
> +        break;
> +    case NM_SHX:
> +    /*case NM_SHXS:*/
> +        gen_load_gpr(t1, rd);
> +        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
> +                           MO_TEUW);
> +        break;
> +    case NM_SWX:
> +    /*case NM_SWXS:*/
> +        gen_load_gpr(t1, rd);
> +        tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx,
> +                           MO_TEUL);
> +        break;

As do these.


r~