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[Qemu-devel] [PULL 7/9] target/mips: Update gen_flt_ldst()
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 7/9] target/mips: Update gen_flt_ldst() |
Date: |
Mon, 25 Jun 2018 22:06:02 +0200 |
From: Yongbok Kim <address@hidden>
Update gen_flt_ldst() in order to reuse the functions for nanoMIPS
Signed-off-by: Yongbok Kim <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 15 +++++++--------
1 file changed, 7 insertions(+), 8 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 2eb211a..e923d27 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -2433,11 +2433,8 @@ static void gen_st_cond (DisasContext *ctx, uint32_t
opc, int rt,
/* Load and store */
static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft,
- int base, int16_t offset)
+ TCGv t0)
{
- TCGv t0 = tcg_temp_new();
-
- gen_base_offset_addr(ctx, t0, base, offset);
/* Don't do NOP if destination is zero: we must perform the actual
memory access. */
switch (opc) {
@@ -2480,15 +2477,15 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t
opc, int ft,
default:
MIPS_INVAL("flt_ldst");
generate_exception_end(ctx, EXCP_RI);
- goto out;
+ break;
}
- out:
- tcg_temp_free(t0);
}
static void gen_cop1_ldst(DisasContext *ctx, uint32_t op, int rt,
int rs, int16_t imm)
{
+ TCGv t0 = tcg_temp_new();
+
if (ctx->CP0_Config1 & (1 << CP0C1_FP)) {
check_cp1_enabled(ctx);
switch (op) {
@@ -2497,11 +2494,13 @@ static void gen_cop1_ldst(DisasContext *ctx, uint32_t
op, int rt,
check_insn(ctx, ISA_MIPS2);
/* Fallthrough */
default:
- gen_flt_ldst(ctx, op, rt, rs, imm);
+ gen_base_offset_addr(ctx, t0, rs, imm);
+ gen_flt_ldst(ctx, op, rt, t0);
}
} else {
generate_exception_err(ctx, EXCP_CpU, 1);
}
+ tcg_temp_free(t0);
}
/* Arithmetic with immediate operand */
--
2.7.4
- [Qemu-devel] [PULL 0/9] Target MIPS queue, 2018-06-25, Aleksandar Markovic, 2018/06/25
- [Qemu-devel] [PULL 9/9] target/mips: Fix gdbstub to read/write 64 bit FP registers, Aleksandar Markovic, 2018/06/25
- [Qemu-devel] [PULL 3/9] hw/mips/mips_malta: don't make bios region 'nomigrate', Aleksandar Markovic, 2018/06/25
- [Qemu-devel] [PULL 8/9] target/mips: Fix data type for offset, Aleksandar Markovic, 2018/06/25
- [Qemu-devel] [PULL 5/9] target/mips: Raise a RI when given fs is n/a from CTC1, Aleksandar Markovic, 2018/06/25
- [Qemu-devel] [PULL 2/9] hw/mips/boston: don't make flash region 'nomigrate', Aleksandar Markovic, 2018/06/25
- [Qemu-devel] [PULL 4/9] hw/pci-host/xilinx-pcie: don't make "io" region be RAM, Aleksandar Markovic, 2018/06/25
- [Qemu-devel] [PULL 6/9] target/mips: Fix microMIPS on reset, Aleksandar Markovic, 2018/06/25
- [Qemu-devel] [PULL 7/9] target/mips: Update gen_flt_ldst(),
Aleksandar Markovic <=
- [Qemu-devel] [PULL 1/9] MAINTAINERS: update target-mips maintainers, Aleksandar Markovic, 2018/06/25
- Re: [Qemu-devel] [PULL 0/9] Target MIPS queue, 2018-06-25, Peter Maydell, 2018/06/26