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[Qemu-devel] [PATCH v3 08/23] target/openrisc: Split out is_user
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v3 08/23] target/openrisc: Split out is_user |
Date: |
Wed, 27 Jun 2018 20:03:15 -0700 |
This allows us to limit the amount of ifdefs and isolate
the test for usermode.
Reviewed-by: Stafford Horne <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
target/openrisc/translate.c | 27 ++++++++++++---------------
1 file changed, 12 insertions(+), 15 deletions(-)
diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c
index a618d39242..db149986af 100644
--- a/target/openrisc/translate.c
+++ b/target/openrisc/translate.c
@@ -50,6 +50,15 @@ typedef struct DisasContext {
target_ulong jmp_pc_imm;
} DisasContext;
+static inline bool is_user(DisasContext *dc)
+{
+#ifdef CONFIG_USER_ONLY
+ return true;
+#else
+ return dc->mem_idx == MMU_USER_IDX;
+#endif
+}
+
/* Include the auto-generated decoder. */
#include "decode.inc.c"
@@ -853,33 +862,25 @@ static bool trans_l_mfspr(DisasContext *dc, arg_l_mfspr
*a, uint32_t insn)
{
check_r0_write(a->d);
-#ifdef CONFIG_USER_ONLY
- gen_illegal_exception(dc);
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
+ if (is_user(dc)) {
gen_illegal_exception(dc);
} else {
TCGv_i32 ti = tcg_const_i32(a->k);
gen_helper_mfspr(cpu_R[a->d], cpu_env, cpu_R[a->d], cpu_R[a->a], ti);
tcg_temp_free_i32(ti);
}
-#endif
return true;
}
static bool trans_l_mtspr(DisasContext *dc, arg_l_mtspr *a, uint32_t insn)
{
-#ifdef CONFIG_USER_ONLY
- gen_illegal_exception(dc);
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
+ if (is_user(dc)) {
gen_illegal_exception(dc);
} else {
TCGv_i32 ti = tcg_const_i32(a->k);
gen_helper_mtspr(cpu_env, cpu_R[a->a], cpu_R[a->b], ti);
tcg_temp_free_i32(ti);
}
-#endif
return true;
}
@@ -1104,16 +1105,12 @@ static bool trans_l_csync(DisasContext *dc, arg_l_csync
*a, uint32_t insn)
static bool trans_l_rfe(DisasContext *dc, arg_l_rfe *a, uint32_t insn)
{
-#ifdef CONFIG_USER_ONLY
- gen_illegal_exception(dc);
-#else
- if (dc->mem_idx == MMU_USER_IDX) {
+ if (is_user(dc)) {
gen_illegal_exception(dc);
} else {
gen_helper_rfe(cpu_env);
dc->base.is_jmp = DISAS_EXIT;
}
-#endif
return true;
}
--
2.17.1
- [Qemu-devel] [PATCH v3 00/23] target/openrisc improvements, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 01/23] target/openrisc: Fix mtspr shadow gprs, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 03/23] target/openrisc: Log interrupts, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 04/23] target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 05/23] target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 06/23] target/openrisc: Fix singlestep_enabled, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 10/23] target/openrisc: Form the spr index from tcg, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 02/23] target/openrisc: Add print_insn_or1k, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 07/23] target/openrisc: Link more translation blocks, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 08/23] target/openrisc: Split out is_user,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 12/23] target/openrisc: Remove indirect function calls for mmu, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 11/23] target/openrisc: Merge tlb allocation into CPUOpenRISCState, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 09/23] target/openrisc: Exit the TB after l.mtspr, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 14/23] target/openrisc: Reduce tlb to a single dimension, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 16/23] target/openrisc: Fix cpu_mmu_index, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 13/23] target/openrisc: Merge mmu_helper.c into mmu.c, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 15/23] target/openrisc: Fix tlb flushing in mtspr, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 19/23] target/openrisc: Increase the TLB size, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 17/23] target/openrisc: Use identical sizes for ITLB and DTLB, Richard Henderson, 2018/06/27
- [Qemu-devel] [PATCH v3 18/23] target/openrisc: Stub out handle_mmu_fault for softmmu, Richard Henderson, 2018/06/27