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[Qemu-devel] [PATCH v3 11/20] kvm: arm64: Helper for computing VTCR_EL2.
From: |
Suzuki K Poulose |
Subject: |
[Qemu-devel] [PATCH v3 11/20] kvm: arm64: Helper for computing VTCR_EL2.SL0 |
Date: |
Fri, 29 Jun 2018 12:15:31 +0100 |
VTCR_EL2 holds the following key stage2 translation table
parameters:
SL0 - Entry level in the page table lookup.
T0SZ - Denotes the size of the memory addressed by the table.
We have been using fixed values for the SL0 depending on the
page size as we have a fixed IPA size. But since we are about
to make it dynamic, we need to calculate the SL0 at runtime
per VM. This patch adds a helper to comput the value of SL0 for
a given IPA.
Cc: Marc Zyngier <address@hidden>
Cc: Christoffer Dall <address@hidden>
Signed-off-by: Suzuki K Poulose <address@hidden>
---
Changes since v2:
- Part 2 of split from VTCR & VTTBR dynamic configuration
---
arch/arm64/include/asm/kvm_arm.h | 35 ++++++++++++++++++++++++++++++++---
1 file changed, 32 insertions(+), 3 deletions(-)
diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
index c557f45..11a7db0 100644
--- a/arch/arm64/include/asm/kvm_arm.h
+++ b/arch/arm64/include/asm/kvm_arm.h
@@ -153,7 +153,8 @@
* 2 level page tables (SL = 1)
*/
#define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_64K | VTCR_EL2_SL0_LVL1)
-#define VTTBR_X_TGRAN_MAGIC 38
+#define VTCR_EL2_TGRAN_SL0_BASE 3UL
+
#elif defined(CONFIG_ARM64_16K_PAGES)
/*
* Stage2 translation configuration:
@@ -161,7 +162,7 @@
* 2 level page tables (SL = 1)
*/
#define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_16K | VTCR_EL2_SL0_LVL1)
-#define VTTBR_X_TGRAN_MAGIC 42
+#define VTCR_EL2_TGRAN_SL0_BASE 3UL
#else /* 4K */
/*
* Stage2 translation configuration:
@@ -169,11 +170,39 @@
* 3 level page tables (SL = 1)
*/
#define VTCR_EL2_TGRAN_FLAGS (VTCR_EL2_TG0_4K | VTCR_EL2_SL0_LVL1)
-#define VTTBR_X_TGRAN_MAGIC 37
+#define VTCR_EL2_TGRAN_SL0_BASE 2UL
#endif
#define VTCR_EL2_FLAGS (VTCR_EL2_COMMON_BITS |
VTCR_EL2_TGRAN_FLAGS)
/*
+ * VTCR_EL2:SL0 indicates the entry level for Stage2 translation.
+ * Interestingly, it depends on the page size.
+ * See D.10.2.110, VTCR_EL2, in ARM DDI 0487B.b
+ *
+ * -----------------------------------------
+ * | Entry level | 4K | 16K/64K |
+ * ------------------------------------------
+ * | Level: 0 | 2 | - |
+ * ------------------------------------------
+ * | Level: 1 | 1 | 2 |
+ * ------------------------------------------
+ * | Level: 2 | 0 | 1 |
+ * ------------------------------------------
+ * | Level: 3 | - | 0 |
+ * ------------------------------------------
+ *
+ * That table roughly translates to :
+ *
+ * SL0(PAGE_SIZE, Entry_level) = SL0_BASE(PAGE_SIZE) - Entry_Level
+ *
+ * Where SL0_BASE(4K) = 2 and SL0_BASE(16K) = 3, SL0_BASE(64K) = 3, provided
+ * we take care of ruling out the unsupported cases and
+ * Entry_Level = 4 - Number_of_levels.
+ *
+ */
+#define VTCR_EL2_SL0(levels) \
+ ((VTCR_EL2_TGRAN_SL0_BASE - (4 - (levels))) << VTCR_EL2_SL0_SHIFT)
+/*
* ARM VMSAv8-64 defines an algorithm for finding the translation table
* descriptors in section D4.2.8 in ARM DDI 0487B.b.
*
--
2.7.4
- [Qemu-devel] [PATCH v3 01/20] virtio: mmio-v1: Validate queue PFN, (continued)
- [Qemu-devel] [PATCH v3 01/20] virtio: mmio-v1: Validate queue PFN, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [PATCH v3 02/20] virtio: pci-legacy: Validate queue pfn, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [PATCH v3 03/20] arm64: Add a helper for PARange to physical shift conversion, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [PATCH v3 04/20] kvm: arm64: Clean up VTCR_EL2 initialisation, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [PATCH v3 05/20] kvm: arm/arm64: Fix stage2_flush_memslot for 4 level page table, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [PATCH v3 06/20] kvm: arm/arm64: Remove spurious WARN_ON, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [PATCH v3 07/20] kvm: arm/arm64: Prepare for VM specific stage2 translations, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [PATCH v3 08/20] kvm: arm/arm64: Abstract stage2 pgd table allocation, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [PATCH v3 10/20] kvm: arm64: Dynamic configuration of VTTBR mask, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [PATCH v3 09/20] kvm: arm64: Make stage2 page table layout dynamic, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [PATCH v3 11/20] kvm: arm64: Helper for computing VTCR_EL2.SL0,
Suzuki K Poulose <=
- [Qemu-devel] [PATCH v3 12/20] kvm: arm64: Add helper for loading the stage2 setting for a VM, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [PATCH v3 14/20] kvm: arm/arm64: Expose supported physical address limit for VM, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [PATCH v3 13/20] kvm: arm64: Configure VTCR per VM, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [PATCH v3 15/20] kvm: arm/arm64: Allow tuning the physical address size for VM, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [PATCH v3 16/20] kvm: arm64: Switch to per VM IPA limit, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [PATCH v3 18/20] kvm: arm64: Add support for handling 52bit IPA, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [PATCH v3 17/20] vgic: Add support for 52bit guest physical address, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [PATCH v3 19/20] kvm: arm64: Allow IPA size supported by the system, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [kvmtool test PATCH 22/24] kvmtool: arm64: Add support for guest physical address size, Suzuki K Poulose, 2018/06/29
- [Qemu-devel] [PATCH v3 20/20] kvm: arm64: Fall back to normal stage2 entry level, Suzuki K Poulose, 2018/06/29