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[Qemu-devel] [PATCH v3 14/20] intc/arm_gic: Wire the vCPU interface
From: |
Luc Michel |
Subject: |
[Qemu-devel] [PATCH v3 14/20] intc/arm_gic: Wire the vCPU interface |
Date: |
Fri, 29 Jun 2018 15:29:48 +0200 |
Add the read/write functions to handle accesses to the vCPU interface.
Those accesses are forwarded to the real CPU interface, with the CPU id
being converted to the corresponding vCPU id (vCPU id = CPU id +
GIC_NCPU).
As for the CPU interface, we create a base region for the vCPU interface
that fetches the current vCPU id using the current_cpu global variable, and
one mirror region per vCPU which maps to that specific vCPU id. This is
required by the GIC architecture specification.
Signed-off-by: Luc Michel <address@hidden>
---
hw/intc/arm_gic.c | 71 ++++++++++++++++++++++++++++++++++++++++++++++-
1 file changed, 70 insertions(+), 1 deletion(-)
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
index 2b1fa280eb..9bbd544a5c 100644
--- a/hw/intc/arm_gic.c
+++ b/hw/intc/arm_gic.c
@@ -1488,6 +1488,46 @@ static MemTxResult gic_do_cpu_write(void *opaque, hwaddr
addr,
GICState *s = *backref;
int id = (backref - s->backref);
return gic_cpu_write(s, id, addr, value, attrs);
+
+}
+
+static MemTxResult gic_thisvcpu_read(void *opaque, hwaddr addr, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
+{
+ GICState *s = (GICState *)opaque;
+
+ return gic_cpu_read(s, gic_get_current_vcpu(s), addr, data, attrs);
+}
+
+static MemTxResult gic_thisvcpu_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size,
+ MemTxAttrs attrs)
+{
+ GICState *s = (GICState *)opaque;
+
+ return gic_cpu_write(s, gic_get_current_vcpu(s), addr, value, attrs);
+}
+
+static MemTxResult gic_do_vcpu_read(void *opaque, hwaddr addr, uint64_t *data,
+ unsigned size, MemTxAttrs attrs)
+{
+ GICState **backref = (GICState **)opaque;
+ GICState *s = *backref;
+ int id = (backref - s->backref);
+
+ return gic_cpu_read(s, id + GIC_NCPU, addr, data, attrs);
+}
+
+static MemTxResult gic_do_vcpu_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size,
+ MemTxAttrs attrs)
+{
+ GICState **backref = (GICState **)opaque;
+ GICState *s = *backref;
+ int id = (backref - s->backref);
+
+ return gic_cpu_write(s, id + GIC_NCPU, addr, value, attrs);
+
}
static const MemoryRegionOps gic_ops[2] = {
@@ -1509,6 +1549,25 @@ static const MemoryRegionOps gic_cpu_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
+static const MemoryRegionOps gic_virt_ops[2] = {
+ {
+ .read_with_attrs = NULL,
+ .write_with_attrs = NULL,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ },
+ {
+ .read_with_attrs = gic_thisvcpu_read,
+ .write_with_attrs = gic_thisvcpu_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ }
+};
+
+static const MemoryRegionOps gic_vcpu_ops = {
+ .read_with_attrs = gic_do_vcpu_read,
+ .write_with_attrs = gic_do_vcpu_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+};
+
static void arm_gic_realize(DeviceState *dev, Error **errp)
{
/* Device instance realize function for the GIC sysbus device */
@@ -1531,7 +1590,7 @@ static void arm_gic_realize(DeviceState *dev, Error
**errp)
}
/* This creates distributor and main CPU interface (s->cpuiomem[0]) */
- gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, NULL);
+ gic_init_irqs_and_mmio(s, gic_set_irq, gic_ops, gic_virt_ops);
/* Extra core-specific regions for the CPU interfaces. This is
* necessary for "franken-GIC" implementations, for example on
@@ -1547,6 +1606,16 @@ static void arm_gic_realize(DeviceState *dev, Error
**errp)
&s->backref[i], "gic_cpu", 0x100);
sysbus_init_mmio(sbd, &s->cpuiomem[i+1]);
}
+
+ if (s->virt_extn) {
+ for (i = 0; i < s->num_cpu; i++) {
+ memory_region_init_io(&s->vcpuiomem[i + 1], OBJECT(s),
+ &gic_vcpu_ops, &s->backref[i],
+ "gic_vcpu", 0x2000);
+ sysbus_init_mmio(sbd, &s->vcpuiomem[i + 1]);
+ }
+ }
+
}
static void arm_gic_class_init(ObjectClass *klass, void *data)
--
2.17.1
- [Qemu-devel] [PATCH v3 09/20] intc/arm_gic: Add virtualization enabled IRQ helper functions, (continued)
- [Qemu-devel] [PATCH v3 09/20] intc/arm_gic: Add virtualization enabled IRQ helper functions, Luc Michel, 2018/06/29
- [Qemu-devel] [PATCH v3 12/20] intc/arm_gic: Implement virtualization extensions in gic_complete_irq, Luc Michel, 2018/06/29
- [Qemu-devel] [PATCH v3 17/20] intc/arm_gic: Implement maintenance interrupt generation, Luc Michel, 2018/06/29
- [Qemu-devel] [PATCH v3 11/20] intc/arm_gic: Implement virtualization extensions in gic_acknowledge_irq, Luc Michel, 2018/06/29
- [Qemu-devel] [PATCH v3 18/20] intc/arm_gic: Improve traces, Luc Michel, 2018/06/29
- [Qemu-devel] [PATCH v3 16/20] intc/arm_gic: Implement gic_update_virt() function, Luc Michel, 2018/06/29
- [Qemu-devel] [PATCH v3 02/20] intc/arm_gic: Refactor operations on the distributor, Luc Michel, 2018/06/29
- [Qemu-devel] [PATCH v3 05/20] intc/arm_gic: Add the virtualization extensions to the GIC state, Luc Michel, 2018/06/29
- [Qemu-devel] [PATCH v3 20/20] arm/virt: Add support for GICv2 virtualization extensions, Luc Michel, 2018/06/29
- [Qemu-devel] [PATCH v3 19/20] xlnx-zynqmp: Improve GIC wiring and MMIO mapping, Luc Michel, 2018/06/29
- [Qemu-devel] [PATCH v3 14/20] intc/arm_gic: Wire the vCPU interface,
Luc Michel <=
- [Qemu-devel] [PATCH v3 08/20] intc/arm_gic: Refactor secure/ns access check in the CPU interface, Luc Michel, 2018/06/29
- [Qemu-devel] [PATCH v3 04/20] vmstate.h: Provide VMSTATE_UINT16_SUB_ARRAY, Luc Michel, 2018/06/29