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[Qemu-devel] [PULL 52/55] target/arm: Fix SVE system register access che
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 52/55] target/arm: Fix SVE system register access checks |
Date: |
Fri, 29 Jun 2018 15:53:44 +0100 |
From: Richard Henderson <address@hidden>
Leave ARM_CP_SVE, removing ARM_CP_FPU; the sve_access_check
produced by the flag already includes fp_access_check. If
we also check ARM_CP_FPU the double fp_access_check asserts.
Reported-by: Laurent Desnogues <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: Philippe Mathieu-Daudé <address@hidden>
Reviewed-by: Peter Maydell <address@hidden>
Reviewed-by: Laurent Desnogues <address@hidden>
Message-id: address@hidden
Signed-off-by: Peter Maydell <address@hidden>
---
target/arm/helper.c | 8 ++++----
target/arm/translate-a64.c | 5 ++---
2 files changed, 6 insertions(+), 7 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 60589b7eaf9..ae70b874c71 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4414,7 +4414,7 @@ static void zcr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static const ARMCPRegInfo zcr_el1_reginfo = {
.name = "ZCR_EL1", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 0, .crn = 1, .crm = 2, .opc2 = 0,
- .access = PL1_RW, .type = ARM_CP_SVE | ARM_CP_FPU,
+ .access = PL1_RW, .type = ARM_CP_SVE,
.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[1]),
.writefn = zcr_write, .raw_writefn = raw_write
};
@@ -4422,7 +4422,7 @@ static const ARMCPRegInfo zcr_el1_reginfo = {
static const ARMCPRegInfo zcr_el2_reginfo = {
.name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
- .access = PL2_RW, .type = ARM_CP_SVE | ARM_CP_FPU,
+ .access = PL2_RW, .type = ARM_CP_SVE,
.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[2]),
.writefn = zcr_write, .raw_writefn = raw_write
};
@@ -4430,14 +4430,14 @@ static const ARMCPRegInfo zcr_el2_reginfo = {
static const ARMCPRegInfo zcr_no_el2_reginfo = {
.name = "ZCR_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 1, .crm = 2, .opc2 = 0,
- .access = PL2_RW, .type = ARM_CP_SVE | ARM_CP_FPU,
+ .access = PL2_RW, .type = ARM_CP_SVE,
.readfn = arm_cp_read_zero, .writefn = arm_cp_write_ignore
};
static const ARMCPRegInfo zcr_el3_reginfo = {
.name = "ZCR_EL3", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 6, .crn = 1, .crm = 2, .opc2 = 0,
- .access = PL3_RW, .type = ARM_CP_SVE | ARM_CP_FPU,
+ .access = PL3_RW, .type = ARM_CP_SVE,
.fieldoffset = offsetof(CPUARMState, vfp.zcr_el[3]),
.writefn = zcr_write, .raw_writefn = raw_write
};
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index f9863408324..45a6c2a3aa1 100644
--- a/target/arm/translate-a64.c
+++ b/target/arm/translate-a64.c
@@ -1633,11 +1633,10 @@ static void handle_sys(DisasContext *s, uint32_t insn,
bool isread,
default:
break;
}
- if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) {
- return;
- }
if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {
return;
+ } else if ((ri->type & ARM_CP_SVE) && !sve_access_check(s)) {
+ return;
}
if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_IO)) {
--
2.17.1
- [Qemu-devel] [PULL 35/55] target/arm: Implement SVE fp complex multiply add, (continued)
- [Qemu-devel] [PULL 35/55] target/arm: Implement SVE fp complex multiply add, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 38/55] target/arm: Implement SVE dot product (vectors), Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 43/55] i.mx7d: Remove unused header files, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 44/55] i.mx7d: Change SRC unimplemented device name from sdma to src, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 34/55] target/arm: Implement SVE floating-point complex add, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 41/55] target/arm: Implement ARMv8.2-DotProd, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 48/55] target/arm: Mark PMINTENSET accesses as possibly doing IO, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 49/55] sd: Don't trace SDRequest crc field, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 45/55] i.mx7d: Change IRQ number type from hwaddr to int, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 51/55] target/arm: Fix SVE signed division vs x86 overflow exception, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 52/55] target/arm: Fix SVE system register access checks,
Peter Maydell <=
- [Qemu-devel] [PULL 47/55] target/arm: Remove redundant DIV detection for KVM, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 31/55] target/arm: Implement SVE floating-point round to integral value, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 40/55] target/arm: Enable SVE for aarch64-linux-user, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 42/55] target/arm: support reading of CNT[VCT|FRQ]_EL0 from user-space, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 46/55] target/arm: Add ARM_FEATURE_V7VE for v7 Virtualization Extensions, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 53/55] target/arm: Prune a57 features from max, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 54/55] target/arm: Prune a15 features from max, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 55/55] target/arm: Add ID_ISAR6, Peter Maydell, 2018/06/29
- [Qemu-devel] [PULL 50/55] sdcard: Use the ldst API, Peter Maydell, 2018/06/29
- Re: [Qemu-devel] [PULL 00/55] target-arm queue, Peter Maydell, 2018/06/30