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[Qemu-devel] [PULL v3 00/25] OpenRISC updates for 3.0
From: |
Stafford Horne |
Subject: |
[Qemu-devel] [PULL v3 00/25] OpenRISC updates for 3.0 |
Date: |
Tue, 3 Jul 2018 22:50:02 +0900 |
Hello Peter,
Trying again to send this series, just one difference here so just sending the
single patch.
Changes since v2:
- Use PAGE_ instead of PROT_ flags in MMU patches to fix windows build.
Please consider for pull:
The following changes since commit 646f34fa5482e495483de230b4cf0f2ae4fd2781:
tcg: Fix --disable-tcg build breakage (2018-07-02 13:42:05 +0100)
are available in the Git repository at:
address@hidden:stffrdhrn/qemu.git tags/pull-or-20180703
for you to fetch changes up to dfc84745bbaa0fea2abc8575dd349f6e4bb7edc7:
target/openrisc: Fix writes to interrupt mask register (2018-07-03 22:40:33
+0900)
----------------------------------------------------------------
OpenRISC cleanups and Fixes for QEMU 3.0
Mostly patches from Richard Henderson fixing multiple things:
* Fix singlestepping in GDB.
* Use more TB linking.
* Fixes to exit TB after updating SPRs to enable registering of state
changes.
* Significant optimizations and refactors to the TLB
* Split out disassembly from translation.
* Add qemu-or1k to qemu-binfmt-conf.sh.
* Implement signal handling for linux-user.
Then there are a few fixups from me:
* Fix delay slot detections to match hardware, this was masking a bug
in the linus kernel.
* Fix stores to the PIC mask register
----------------------------------------------------------------
Richard Henderson (23):
target/openrisc: Fix mtspr shadow gprs
target/openrisc: Add print_insn_or1k
target/openrisc: Log interrupts
target/openrisc: Remove DISAS_JUMP & DISAS_TB_JUMP
target/openrisc: Use exit_tb instead of CPU_INTERRUPT_EXITTB
target/openrisc: Fix singlestep_enabled
target/openrisc: Link more translation blocks
target/openrisc: Split out is_user
target/openrisc: Exit the TB after l.mtspr
target/openrisc: Form the spr index from tcg
target/openrisc: Merge tlb allocation into CPUOpenRISCState
target/openrisc: Remove indirect function calls for mmu
target/openrisc: Merge mmu_helper.c into mmu.c
target/openrisc: Reduce tlb to a single dimension
target/openrisc: Fix tlb flushing in mtspr
target/openrisc: Fix cpu_mmu_index
target/openrisc: Use identical sizes for ITLB and DTLB
target/openrisc: Stub out handle_mmu_fault for softmmu
target/openrisc: Increase the TLB size
target/openrisc: Reorg tlb lookup
target/openrisc: Add support in scripts/qemu-binfmt-conf.sh
linux-user: Implement signals for openrisc
linux-user: Fix struct sigaltstack for openrisc
Stafford Horne (2):
target/openrisc: Fix delay slot exception flag to match spec
target/openrisc: Fix writes to interrupt mask register
linux-user/openrisc/signal.c | 217 ++++++++-----------
linux-user/openrisc/target_signal.h | 2 +-
linux-user/openrisc/target_syscall.h | 28 +--
linux-user/signal.c | 2 +-
scripts/qemu-binfmt-conf.sh | 10 +-
target/openrisc/Makefile.objs | 5 +-
target/openrisc/cpu.c | 17 +-
target/openrisc/cpu.h | 61 +++---
target/openrisc/disas.c | 170 +++++++++++++++
target/openrisc/helper.h | 4 +-
target/openrisc/interrupt.c | 55 +++--
target/openrisc/interrupt_helper.c | 35 +---
target/openrisc/machine.c | 44 +---
target/openrisc/mmu.c | 279 +++++++++---------------
target/openrisc/mmu_helper.c | 40 ----
target/openrisc/sys_helper.c | 84 ++++----
target/openrisc/translate.c | 303 ++++++++++-----------------
17 files changed, 603 insertions(+), 753 deletions(-)
create mode 100644 target/openrisc/disas.c
delete mode 100644 target/openrisc/mmu_helper.c
--
2.17.0
- [Qemu-devel] [PULL v3 00/25] OpenRISC updates for 3.0,
Stafford Horne <=