Re: [Qemu-devel] [PATCH 1/2] nvic: Handle ARMv6-M SCS reserved registers

[Julia Suvorova]

On 05.07.2018 13:54, Peter Maydell wrote:
> On 4 July 2018 at 20:58, Julia Suvorova <address@hidden> wrote:
> > Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1.
> > All reserved registers are RAZ/WI.
> >
> > Signed-off-by: Julia Suvorova <address@hidden>
> > ---
> >   hw/intc/armv7m_nvic.c | 69 +++++++++++++++++++++++++++++++++++--------
> >   1 file changed, 57 insertions(+), 12 deletions(-)
>
> Hi; this patch is generally good, but I have a couple of comments
> below, and in most (but not all) of these cases we should be
> checking the ARM_FEATURE_M_MAIN bit rather than ARM_FEATURE_V7 --
> I've annotated which should be which.

Thank you for the review. I did not dare to set the ARM_FEATURE_M_MAIN,
because I was not completely sure about the v8M behavior in certain cases.
I'll update the code taking into account all the comments, and send v2.

Best regards, Julia Suvorova.