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[Qemu-devel] [PULL 8/8] accel/tcg: Assert that tlb fill gave us a valid
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 8/8] accel/tcg: Assert that tlb fill gave us a valid TLB entry |
Date: |
Mon, 16 Jul 2018 17:43:00 +0100 |
In commit 4b1a3e1e34ad97 we added a check for whether the TLB entry
we had following a tlb_fill had the INVALID bit set. This could
happen in some circumstances because a stale or wrong TLB entry was
pulled out of the victim cache. However, after commit
68fea038553039e (which prevents stale entries being in the victim
cache) and the previous commit (which ensures we don't incorrectly
hit in the victim cache)) this should never be possible.
Drop the check on TLB_INVALID_MASK from the "is this a TLB_RECHECK?"
condition, and instead assert that the tlb fill procedure has given
us a valid TLB entry (or longjumped out with a guest exception).
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
accel/tcg/cputlb.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c
index 2d5fb15d9a3..563fa30117e 100644
--- a/accel/tcg/cputlb.c
+++ b/accel/tcg/cputlb.c
@@ -970,10 +970,10 @@ tb_page_addr_t get_page_addr_code(CPUArchState *env,
target_ulong addr)
if (!VICTIM_TLB_HIT(addr_code, addr)) {
tlb_fill(ENV_GET_CPU(env), addr, 0, MMU_INST_FETCH, mmu_idx, 0);
}
+ assert(tlb_hit(env->tlb_table[mmu_idx][index].addr_code, addr));
}
- if (unlikely((env->tlb_table[mmu_idx][index].addr_code &
- (TLB_RECHECK | TLB_INVALID_MASK)) == TLB_RECHECK)) {
+ if (unlikely(env->tlb_table[mmu_idx][index].addr_code & TLB_RECHECK)) {
/*
* This is a TLB_RECHECK access, where the MMU protection
* covers a smaller range than a target page, and we must
--
2.17.1
- [Qemu-devel] [PULL 0/8] target-arm queue, Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 3/8] hw/intc/arm_gic: Check interrupt number in gic_deactivate_irq(), Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 4/8] hw/intc/arm_gic: Fix handling of GICD_ITARGETSR, Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 2/8] aspeed: Implement write-1-{set, clear} for AST2500 strapping, Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 1/8] target/arm: Fix LD1W and LDFF1W (scalar plus vector), Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 5/8] hw/arm/bcm2836: Mark the bcm2836 / bcm2837 devices with user_creatable = false, Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 8/8] accel/tcg: Assert that tlb fill gave us a valid TLB entry,
Peter Maydell <=
- [Qemu-devel] [PULL 6/8] bcm2835_aux: Swap RX and TX interrupt assignments, Peter Maydell, 2018/07/16
- [Qemu-devel] [PULL 7/8] accel/tcg: Use correct test when looking in victim TLB for code, Peter Maydell, 2018/07/16
- Re: [Qemu-devel] [PULL 0/8] target-arm queue, Peter Maydell, 2018/07/17