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Re: [Qemu-devel] [PATCH v3 25/40] target/mips: Add updating CP0 BadInstr
From: |
Richard Henderson |
Subject: |
Re: [Qemu-devel] [PATCH v3 25/40] target/mips: Add updating CP0 BadInstrX register for nanoMIPs only |
Date: |
Mon, 23 Jul 2018 09:35:48 -0700 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.9.1 |
On 07/19/2018 05:54 AM, Stefan Markovic wrote:
> From: Stefan Markovic <address@hidden>
>
> Signed-off-by: Yongbok Kim <address@hidden>
> Signed-off-by: Aleksandar Markovic <address@hidden>
> Signed-off-by: Stefan Markovic <address@hidden>
> ---
> target/mips/helper.c | 6 ++++++
> 1 file changed, 6 insertions(+)
>
> diff --git a/target/mips/helper.c b/target/mips/helper.c
> index 5299f21..9535131 100644
> --- a/target/mips/helper.c
> +++ b/target/mips/helper.c
> @@ -695,6 +695,12 @@ static inline void set_badinstr_registers(CPUMIPSState
> *env)
> instr |= cpu_lduw_code(env, env->active_tc.PC + 2);
> }
> env->CP0_BadInstr = instr;
> +
> + if ((env->insn_flags & ISA_NANOMIPS32) &&
> + ((instr & 0xFC000000) == 0x60000000)) {
> + instr = cpu_lduw_code(env, env->active_tc.PC + 4) << 16;
> + env->CP0_BadInstrX = instr;
> + }
The nanomips condition has been checked just above.
This patch should probably be merged with 24/40.
r~
- [Qemu-devel] [PATCH v3 06/40] target/mips: Add emulation of misc nanoMIPS 16-bit instructions, (continued)
- [Qemu-devel] [PATCH v3 06/40] target/mips: Add emulation of misc nanoMIPS 16-bit instructions, Stefan Markovic, 2018/07/19
- [Qemu-devel] [PATCH v3 14/40] target/mips: Add emulation of misc nanoMIPS instructions (pool32axf), Stefan Markovic, 2018/07/19
- [Qemu-devel] [PATCH v3 38/40] gdbstub: Disable handling of nanoMIPS ISA bit in the MIPS gdbstub, Stefan Markovic, 2018/07/19
- [Qemu-devel] [PATCH v3 34/40] linux-user: Don't check FCR31_NAN2008 bit for nanoMIPS, Stefan Markovic, 2018/07/19
- [Qemu-devel] [PATCH v3 25/40] target/mips: Add updating CP0 BadInstrX register for nanoMIPs only, Stefan Markovic, 2018/07/19
- Re: [Qemu-devel] [PATCH v3 25/40] target/mips: Add updating CP0 BadInstrX register for nanoMIPs only,
Richard Henderson <=
- [Qemu-devel] [PATCH v3 35/40] mips_malta: Add basic nanoMIPS boot code for MIPS' Malta, Stefan Markovic, 2018/07/19
- [Qemu-devel] [PATCH v3 27/40] target/mips: Adjust behavior of Config3's ISAOnExc bit for nanoMIPS, Stefan Markovic, 2018/07/19
- [Qemu-devel] [PATCH v3 37/40] mips_malta: Fix semihosting argument passing for nanoMIPS bare metal, Stefan Markovic, 2018/07/19
- [Qemu-devel] [PATCH v3 32/40] elf: Add nanoMIPS specific variations in ELF header fields, Stefan Markovic, 2018/07/19
- [Qemu-devel] [PATCH v3 02/40] target/mips: Add nanoMIPS base instruction set opcodes, Stefan Markovic, 2018/07/19
- [Qemu-devel] [PATCH v3 26/40] target/mips: Implement CP0 Config0.WR bit functionality, Stefan Markovic, 2018/07/19