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[Qemu-devel] [PATCH 06/99] tcg/arm: Fix memory barrier encoding
From: |
Michael Roth |
Subject: |
[Qemu-devel] [PATCH 06/99] tcg/arm: Fix memory barrier encoding |
Date: |
Mon, 23 Jul 2018 15:16:15 -0500 |
From: Henry Wertz <address@hidden>
I found with qemu 2.11.x or newer that I would get an illegal instruction
error running some Intel binaries on my ARM chromebook. On investigation,
I found it was quitting on memory barriers.
qemu instruction:
mb $0x31
was translating as:
0x604050cc: 5bf07ff5 blpl #0x600250a8
After patch it gives:
0x604050cc: f57ff05b dmb ish
In short, I found INSN_DMB_ISH (memory barrier for ARMv7) appeared to be
correct based on online docs, but due to some endian-related shenanigans it
had to be byte-swapped to suit qemu; it appears INSN_DMB_MCR (memory
barrier for ARMv6) also should be byte swapped (and this patch does so).
I have not checked for correctness of aarch64's barrier instruction.
Cc: address@hidden
Reviewed-by: Peter Maydell <address@hidden>
Signed-off-by: Henry Wertz <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
(cherry picked from commit 3f814b803797c007abfe5c4041de754e01723031)
Signed-off-by: Michael Roth <address@hidden>
---
tcg/arm/tcg-target.inc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/arm/tcg-target.inc.c b/tcg/arm/tcg-target.inc.c
index dc83f3e5be..56a32a470f 100644
--- a/tcg/arm/tcg-target.inc.c
+++ b/tcg/arm/tcg-target.inc.c
@@ -159,8 +159,8 @@ typedef enum {
INSN_STRD_IMM = 0x004000f0,
INSN_STRD_REG = 0x000000f0,
- INSN_DMB_ISH = 0x5bf07ff5,
- INSN_DMB_MCR = 0xba0f07ee,
+ INSN_DMB_ISH = 0xf57ff05b,
+ INSN_DMB_MCR = 0xee070fba,
/* Architected nop introduced in v6k. */
/* ??? This is an MSR (imm) 0,0,0 insn. Anyone know if this
--
2.17.1
- [Qemu-devel] [PATCH 05/99] s390-ccw: force diag 308 subcode to unsigned long, (continued)
- [Qemu-devel] [PATCH 05/99] s390-ccw: force diag 308 subcode to unsigned long, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 62/99] riscv: requires libfdt, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 63/99] nbd/client: Relax handling of large NBD_CMD_BLOCK_STATUS reply, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 64/99] tcg/i386: Fix dup_vec in non-AVX2 codepath, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 65/99] softfloat: Handle default NaN mode after pickNaNMulAdd, not before, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 66/99] tcg: Limit the number of ops in a TB, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 67/99] RISC-V: Minimal QEMU 2.12 fix for sifive_u machine, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 68/99] blockjob: expose error string via query, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 69/99] target/arm: Fix fp_status_f16 tininess before rounding, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 70/99] fpu/softfloat: Don't set Invalid for float-to-int(MAXINT), Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 06/99] tcg/arm: Fix memory barrier encoding,
Michael Roth <=
- [Qemu-devel] [PATCH 72/99] target/arm: Implement vector shifted FCVT for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 71/99] target/arm: Implement vector shifted SCVF/UCVF for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 73/99] target/arm: Fix float16 to/from int16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 74/99] target/arm: Clear SVE high bits for FMOV, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 76/99] target/arm: Implement FMOV (general) for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 77/99] target/arm: Implement FCVT (scalar, integer) for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 75/99] fpu/softfloat: Fix conversion from uint64 to float128, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 78/99] target/arm: Implement FCVT (scalar, fixed-point) for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 80/99] target/arm: Implement FP data-processing (2 source) for fp16, Michael Roth, 2018/07/23
- [Qemu-devel] [PATCH 79/99] target/arm: Introduce and use read_fp_hreg, Michael Roth, 2018/07/23